{"id":"https://openalex.org/W2789984124","doi":"https://doi.org/10.1145/3177540.3177557","title":"Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution","display_name":"Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution","publication_year":2018,"publication_date":"2018-03-16","ids":{"openalex":"https://openalex.org/W2789984124","doi":"https://doi.org/10.1145/3177540.3177557","mag":"2789984124"},"language":"en","primary_location":{"id":"doi:10.1145/3177540.3177557","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3177540.3177557","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Andr\u00e9 Reis","raw_affiliation_strings":["UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5065397615"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.01074264,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"58","last_page":"59"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7658959627151489},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.691730260848999},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.654510498046875},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6458845734596252},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5663937926292419},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5363143086433411},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5361694097518921},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5004887580871582},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4996340274810791},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41152238845825195},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39842474460601807},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.35057443380355835},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22416239976882935},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1829187273979187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15806010365486145},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13680309057235718}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7658959627151489},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.691730260848999},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.654510498046875},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6458845734596252},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5663937926292419},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5363143086433411},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5361694097518921},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5004887580871582},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4996340274810791},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41152238845825195},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39842474460601807},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.35057443380355835},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22416239976882935},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1829187273979187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15806010365486145},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13680309057235718}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3177540.3177557","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3177540.3177557","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.550000011920929}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1985457698","https://openalex.org/W2025617772","https://openalex.org/W2054095206","https://openalex.org/W2137753585","https://openalex.org/W2770713837"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2526300902","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2170504327","https://openalex.org/W2766377030","https://openalex.org/W4249951793","https://openalex.org/W1990901299","https://openalex.org/W2542337934"],"abstract_inverted_index":{"This":[0],"paper":[1],"discusses":[2],"directions":[3],"for":[4],"a":[5,11,34],"VLSI":[6],"design":[7,52],"flow":[8],"based":[9],"on":[10],"novel":[12],"paradigm":[13,56],"of":[14],"local":[15],"logic":[16,38],"computation":[17],"and":[18,40],"global":[19],"signal":[20],"distribution.":[21],"In":[22],"the":[23,44],"last":[24],"years":[25],"there":[26],"has":[27],"been":[28],"an":[29],"increasing":[30],"effort":[31],"to":[32,46,62],"perform":[33],"better":[35],"integration":[36],"between":[37],"synthesis":[39],"physical":[41],"design,":[42],"with":[43],"aim":[45],"bring":[47],"technology":[48],"information":[49],"into":[50],"early":[51],"steps.":[53],"The":[54],"proposed":[55],"shift":[57],"can":[58],"be":[59],"very":[60],"helpful":[61],"attain":[63],"this":[64],"integration.":[65]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}