{"id":"https://openalex.org/W2789489838","doi":"https://doi.org/10.1145/3177540.3177542","title":"Challenges in Large FPGA-based Logic Emulation Systems","display_name":"Challenges in Large FPGA-based Logic Emulation Systems","publication_year":2018,"publication_date":"2018-03-16","ids":{"openalex":"https://openalex.org/W2789489838","doi":"https://doi.org/10.1145/3177540.3177542","mag":"2789489838"},"language":"en","primary_location":{"id":"doi:10.1145/3177540.3177542","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3177540.3177542","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081272390","display_name":"William N. N. Hung","orcid":"https://orcid.org/0000-0001-5024-7544"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William N.N. Hung","raw_affiliation_strings":["Synopsys, Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111538908","display_name":"Richard Sun","orcid":"https://orcid.org/0009-0003-3924-2154"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Richard Sun","raw_affiliation_strings":["Synopsys, Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":4.1858,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.95142457,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"26","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.8036580085754395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7183079123497009},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7095789313316345},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6268706321716309},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6177785992622375},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5958267450332642},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5922456383705139},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.5553002953529358},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5501287579536438},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5446975827217102},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49498480558395386},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.48450228571891785},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.48255079984664917},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.47657060623168945},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.47644975781440735},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.46987801790237427},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.4630906879901886},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4576011002063751},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4269682765007019},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.42363080382347107},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23692965507507324},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17162001132965088},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08342510461807251},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07921755313873291}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.8036580085754395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7183079123497009},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7095789313316345},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6268706321716309},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6177785992622375},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5958267450332642},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5922456383705139},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.5553002953529358},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5501287579536438},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5446975827217102},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49498480558395386},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.48450228571891785},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48255079984664917},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.47657060623168945},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.47644975781440735},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.46987801790237427},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.4630906879901886},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4576011002063751},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4269682765007019},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.42363080382347107},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23692965507507324},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17162001132965088},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08342510461807251},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07921755313873291},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3177540.3177542","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3177540.3177542","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2012012429","https://openalex.org/W2053808610","https://openalex.org/W2056692632","https://openalex.org/W2115294662","https://openalex.org/W2121066557","https://openalex.org/W2121290396","https://openalex.org/W2148658001","https://openalex.org/W2150071934","https://openalex.org/W2157160989","https://openalex.org/W2232099603"],"related_works":["https://openalex.org/W2122108735","https://openalex.org/W2399012645","https://openalex.org/W1928822090","https://openalex.org/W2121635307","https://openalex.org/W1504237414","https://openalex.org/W2886316328","https://openalex.org/W3097333598","https://openalex.org/W2041277225","https://openalex.org/W2113539181","https://openalex.org/W2360492460"],"abstract_inverted_index":{"Functional":[0],"verification":[1,21,24],"is":[2],"an":[3],"important":[4],"aspect":[5],"of":[6,37,44],"electronic":[7],"design":[8,58],"automation.":[9],"Traditionally,":[10],"simulation":[11],"at":[12],"the":[13,18,42,50,57,114],"register":[14],"transfer-level":[15],"has":[16],"been":[17,31],"mainstream":[19],"functional":[20,69],"approach.":[22],"Formal":[23],"and":[25,76,88,105],"various":[26,107],"static":[27],"analysis":[28],"checkers":[29],"have":[30,65],"used":[32],"to":[33,54,73,84],"complement":[34],"specific":[35],"corners":[36],"logic":[38,63,85,103],"simulation.":[39],"However,":[40],"as":[41],"size":[43],"IC":[45],"designs":[46],"grow":[47],"exponentially,":[48],"all":[49],"above":[51],"approaches":[52,83],"fail":[53],"scale":[55],"with":[56],"growth.":[59],"In":[60,94],"recent":[61],"years,":[62],"emulation":[64,104],"gained":[66],"popularity":[67],"in":[68,110],"verification,":[70],"partly":[71],"due":[72],"their":[74],"performance":[75],"scalability":[77],"benefits.":[78],"There":[79],"are":[80],"two":[81],"main":[82],"emulation:":[86],"ASIC":[87],"commercial":[89,100],"field-programmable":[90],"gate":[91],"array":[92],"(FPGA).":[93],"this":[95,111],"paper,":[96],"we":[97],"focus":[98],"on":[99],"FPGA":[101],"based":[102],"present":[106],"challenging":[108],"problems":[109],"area":[112],"for":[113],"academic":[115],"community.":[116]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}