{"id":"https://openalex.org/W2791212328","doi":"https://doi.org/10.1145/3174243.3174976","title":"Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary","display_name":"Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2791212328","doi":"https://doi.org/10.1145/3174243.3174976","mag":"2791212328"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174976","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071123240","display_name":"Mat\u011bj Bart\u00edk","orcid":"https://orcid.org/0000-0002-6035-1019"},"institutions":[{"id":"https://openalex.org/I54634078","display_name":"Czech Education and Scientific Network","ror":"https://ror.org/050dkka69","country_code":"CZ","type":"other","lineage":["https://openalex.org/I54634078"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Mat\u011bj Bart\u00edk","raw_affiliation_strings":["CESNET a.l.e., Prague, Czech Rep"],"affiliations":[{"raw_affiliation_string":"CESNET a.l.e., Prague, Czech Rep","institution_ids":["https://openalex.org/I54634078"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051629625","display_name":"Sven Ubik","orcid":"https://orcid.org/0000-0003-2272-6454"},"institutions":[{"id":"https://openalex.org/I54634078","display_name":"Czech Education and Scientific Network","ror":"https://ror.org/050dkka69","country_code":"CZ","type":"other","lineage":["https://openalex.org/I54634078"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Sven Ubik","raw_affiliation_strings":["CESNET a.l.e., Prague, Czech Rep"],"affiliations":[{"raw_affiliation_string":"CESNET a.l.e., Prague, Czech Rep","institution_ids":["https://openalex.org/I54634078"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003084750","display_name":"Pavel Kubal\u00edk","orcid":null},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Pavel Kubal\u00edk","raw_affiliation_strings":["CTU FIT, Prague, Czech Rep"],"affiliations":[{"raw_affiliation_string":"CTU FIT, Prague, Czech Rep","institution_ids":["https://openalex.org/I44504214"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112638441","display_name":"Tom\u00e1\u0161 Bene\u0161","orcid":null},"institutions":[{"id":"https://openalex.org/I44504214","display_name":"Czech Technical University in Prague","ror":"https://ror.org/03kqpb082","country_code":"CZ","type":"education","lineage":["https://openalex.org/I44504214"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Tom\u00e1\u0161 Bene\u0161","raw_affiliation_strings":["CTU FIT, Prague, Czech Rep"],"affiliations":[{"raw_affiliation_string":"CTU FIT, Prague, Czech Rep","institution_ids":["https://openalex.org/I44504214"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5071123240"],"corresponding_institution_ids":["https://openalex.org/I54634078"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.03116597,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"290","last_page":"290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.965499997138977,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8037503957748413},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7937872409820557},{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.7698489427566528},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5192139744758606},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5161015391349792},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.42704084515571594},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.41766414046287537},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37885376811027527},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37403926253318787},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3593195676803589},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3468679189682007},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2754408121109009},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09625712037086487}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8037503957748413},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7937872409820557},{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.7698489427566528},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5192139744758606},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5161015391349792},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.42704084515571594},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.41766414046287537},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37885376811027527},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37403926253318787},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3593195676803589},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3468679189682007},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2754408121109009},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09625712037086487},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3174243.3174976","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2948148442","https://openalex.org/W2461250372","https://openalex.org/W2394342941","https://openalex.org/W2169853506","https://openalex.org/W2547124190","https://openalex.org/W2350586049","https://openalex.org/W2385628723","https://openalex.org/W2057878850","https://openalex.org/W2169871401","https://openalex.org/W3008492011"],"abstract_inverted_index":{"This":[0,84],"paper":[1],"presents":[2],"a":[3,30,38],"performance":[4,67],"comparison":[5],"of":[6,9,11,29,56,69],"various":[7],"approaches":[8],"realization":[10],"status":[12,34],"register":[13,35],"suitable":[14],"for":[15,40,80,99],"maintaining":[16],"(in)valid":[17],"bits":[18],"in":[19,24,74],"mid-density":[20],"memory":[21],"structures":[22],"implemented":[23],"Xilinx":[25,75],"FPGAs.":[26],"An":[27],"example":[28],"such":[31],"structure":[32],"with":[33,59],"could":[36],"be":[37,51],"dictionary":[39,48],"Lempel-Ziv":[41],"based":[42],"lossless":[43],"compression":[44],"algorithms":[45],"where":[46],"the":[47,57,81,91,104],"has":[49,71,86],"to":[50],"initialized":[52],"before":[53],"each":[54],"run":[55],"algorithm":[58],"minimum":[60],"time":[61],"and":[62,77,96,102],"logic":[63],"resources":[64],"consumption.":[65],"The":[66],"evaluation":[68],"designs":[70],"been":[72,87],"made":[73],"ISE":[76],"Vivado":[78],"toolkits":[79],"Virtex-7":[82],"FPGA.":[83],"research":[85],"partially":[88],"supported":[89],"by":[90,103],"CTU":[92],"project":[93,105],"SGS17/017/OHK3/1T/18":[94],"\"Dependable":[95],"attack-resistant":[97],"architectures":[98],"programmable":[100],"devices\"":[101],"\"E-infrastructure":[106],"CESNET":[107],"\"modernization\"":[108],"no.":[109],"CZ.02.1.01/0.0/0.0/16":[110],"013/0001797.":[111]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}