{"id":"https://openalex.org/W2789564496","doi":"https://doi.org/10.1145/3174243.3174272","title":"Improving FPGA Performance with a S44 LUT Structure","display_name":"Improving FPGA Performance with a S44 LUT Structure","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2789564496","doi":"https://doi.org/10.1145/3174243.3174272","mag":"2789564496"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174272","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174272","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100852727","display_name":"Wenyi Feng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110187","display_name":"Microsemi (United States)","ror":"https://ror.org/01mvkzj41","country_code":"US","type":"company","lineage":["https://openalex.org/I4210110187"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wenyi Feng","raw_affiliation_strings":["Microsemi Corporation SOC Products Group, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Microsemi Corporation SOC Products Group, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210110187"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076157491","display_name":"Jonathan Greene","orcid":"https://orcid.org/0000-0002-7038-6629"},"institutions":[{"id":"https://openalex.org/I4210110187","display_name":"Microsemi (United States)","ror":"https://ror.org/01mvkzj41","country_code":"US","type":"company","lineage":["https://openalex.org/I4210110187"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Greene","raw_affiliation_strings":["Microsemi Corporation SOC Products Group, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Microsemi Corporation SOC Products Group, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210110187"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["University of California, Berkeley, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100852727"],"corresponding_institution_ids":["https://openalex.org/I4210110187"],"apc_list":null,"apc_paid":null,"fwci":1.9567,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.86648007,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"61","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.9318094253540039},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.735943078994751},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6963484287261963},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6303861141204834},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.5956407189369202},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5222000479698181},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.4652358591556549},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4553740918636322},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41535037755966187},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39182743430137634},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3304404020309448},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27160096168518066},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13130038976669312}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.9318094253540039},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.735943078994751},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6963484287261963},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6303861141204834},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.5956407189369202},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5222000479698181},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.4652358591556549},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4553740918636322},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41535037755966187},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39182743430137634},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3304404020309448},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27160096168518066},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13130038976669312},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3174243.3174272","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174272","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1991576731","https://openalex.org/W2005602803","https://openalex.org/W2023428606","https://openalex.org/W2049121968","https://openalex.org/W2078644645","https://openalex.org/W2100955320","https://openalex.org/W2113645429","https://openalex.org/W2116094656","https://openalex.org/W2118988958","https://openalex.org/W2126814059","https://openalex.org/W2151791681","https://openalex.org/W2290686466","https://openalex.org/W2742222439","https://openalex.org/W3147706417","https://openalex.org/W6631201520","https://openalex.org/W6669805704"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W2745001401","https://openalex.org/W4321353415","https://openalex.org/W2130974462","https://openalex.org/W972276598","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441"],"abstract_inverted_index":{"FPGA":[0],"performance":[1,132],"depends":[2],"in":[3,78,90],"part":[4],"on":[5],"the":[6,20,67,95,131,138],"choice":[7],"of":[8,60,73,84,98,133,144],"basic":[9],"logic":[10],"cell.":[11],"Previous":[12],"work":[13],"dating":[14],"back":[15],"to":[16,117,124],"1999-2005":[17],"found":[18],"that":[19,41,66,122],"best":[21],"look-up":[22],"table":[23],"(LUT)":[24],"sizes":[25],"for":[26,34,38],"area-delay":[27],"product":[28],"are":[29],"4-6,":[30],"with":[31,56],"4":[32],"better":[33],"area":[35,139],"and":[36,101,113,140],"6":[37],"performance.":[39],"Since":[40],"time":[42],"several":[43],"things":[44],"have":[45,93],"changed.":[46],"A":[47],"new":[48],"'LUT":[49],"structure'":[50],"mapping":[51,123],"technique":[52],"can":[53,129],"target":[54],"cells":[55],"a":[57,80,125],"larger":[58],"number":[59],"inputs":[61],"(cut":[62],"size)":[63],"without":[64],"assuming":[65],"cell":[68],"implements":[69],"all":[70],"possible":[71],"functions":[72],"those":[74],"inputs.":[75],"We":[76],"consider":[77],"particular":[79],"7-input":[81,126],"function":[82],"composed":[83],"two":[85],"tightly-coupled":[86],"4-input":[87,145],"LUTs.":[88,146],"Changes":[89],"process":[91],"technology":[92],"increased":[94],"relative":[96],"importance":[97],"wiring":[99],"delay":[100],"configuration":[102],"memory":[103,114],"area.":[104],"Finally,":[105],"modern":[106],"benchmark":[107],"applications":[108],"include":[109],"carry":[110],"chains,":[111],"math":[112],"blocks.":[115],"Due":[116],"these":[118],"changes,":[119],"we":[120],"show":[121],"LUT":[127],"structure":[128],"approach":[130],"6-input":[134],"LUTs":[135],"while":[136],"retaining":[137],"static":[141],"power":[142],"advantage":[143]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}