{"id":"https://openalex.org/W2768439981","doi":"https://doi.org/10.1145/3174243.3174270","title":"P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs","display_name":"P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2768439981","doi":"https://doi.org/10.1145/3174243.3174270","mag":"2768439981"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174270","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174270","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/1711.06613","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023229834","display_name":"Jeferson Santiago da Silva","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Jeferson Santiago da Silva","raw_affiliation_strings":["Polytechnique Montr\u00e9al, Montr\u00e9al, PQ, Canada"],"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al, Montr\u00e9al, PQ, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111748115","display_name":"Fran\u00e7ois-Raymond Boyer","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Fran\u00e7ois-Raymond Boyer","raw_affiliation_strings":["Polytechnique Montr\u00e9al, Montr\u00e9al, PQ, Canada"],"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al, Montr\u00e9al, PQ, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032933923","display_name":"J. M. Pierre Langlois","orcid":"https://orcid.org/0000-0003-1721-2520"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J.M. Pierre Langlois","raw_affiliation_strings":["Polytechnique Montr\u00e9al, Montr\u00e9al, PQ, Canada"],"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al, Montr\u00e9al, PQ, Canada","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5023229834"],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":4.6814,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.95151399,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"147","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10847","display_name":"Advanced Optical Network Technologies","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8854320645332336},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7383071184158325},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.6767503023147583},{"id":"https://openalex.org/keywords/packet-processing","display_name":"Packet processing","score":0.6218057870864868},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5916308164596558},{"id":"https://openalex.org/keywords/parsing","display_name":"Parsing","score":0.5704091787338257},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.4324149191379547},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.42340564727783203},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37935593724250793},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3589543402194977},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35312336683273315},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2747936248779297},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1651667356491089},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12069687247276306}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8854320645332336},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7383071184158325},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.6767503023147583},{"id":"https://openalex.org/C2779581428","wikidata":"https://www.wikidata.org/wiki/Q7122997","display_name":"Packet processing","level":3,"score":0.6218057870864868},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5916308164596558},{"id":"https://openalex.org/C186644900","wikidata":"https://www.wikidata.org/wiki/Q194152","display_name":"Parsing","level":2,"score":0.5704091787338257},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.4324149191379547},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.42340564727783203},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37935593724250793},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3589543402194977},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35312336683273315},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2747936248779297},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1651667356491089},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12069687247276306},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3174243.3174270","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174270","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:1711.06613","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1711.06613","pdf_url":"https://arxiv.org/pdf/1711.06613","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"pmh:oai:publications.polymtl.ca:39943","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/39943/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:1711.06613","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1711.06613","pdf_url":"https://arxiv.org/pdf/1711.06613","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1994327700","https://openalex.org/W1994926493","https://openalex.org/W2022758041","https://openalex.org/W2040678819","https://openalex.org/W2077150300","https://openalex.org/W2134519279","https://openalex.org/W2142987071","https://openalex.org/W2169485114","https://openalex.org/W2510309737","https://openalex.org/W2607067159","https://openalex.org/W4237967441","https://openalex.org/W4247384102","https://openalex.org/W4248966981","https://openalex.org/W4253731216"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2540393334","https://openalex.org/W1983570530","https://openalex.org/W2062932566","https://openalex.org/W2390042878","https://openalex.org/W2085828379","https://openalex.org/W2271847574","https://openalex.org/W2746234147"],"abstract_inverted_index":{"Packet":[0,9],"parsing":[1,63],"is":[2,87,99,121],"a":[3,81,102,108,112,139,145],"key":[4],"step":[5],"in":[6,11,67,144],"SDN-aware":[7],"devices.":[8],"parsers":[10,78],"SDN":[12,68],"networks":[13],"need":[14],"to":[15,21,42,64,107,162],"be":[16,43,65],"both":[17],"reconfigurable":[18],"and":[19,27,74,89,131,155],"fast,":[20],"support":[22],"the":[23,28,44,124,151,156,163],"evolving":[24],"network":[25],"protocols":[26],"increasing":[29],"multi-gigabit":[30],"data":[31,142],"rates.":[32],"The":[33,96,118],"combination":[34],"of":[35,114],"packet":[36,62,77,82],"processing":[37,83],"languages":[38],"with":[39,133],"FPGAs":[40],"seems":[41],"perfect":[45],"match":[46],"for":[47,60],"these":[48],"requirements.":[49],"In":[50],"this":[51],"work,":[52],"we":[53],"develop":[54],"an":[55],"open-source":[56],"FPGA-based":[57],"configurable":[58],"architecture":[59,86,137],"arbitrary":[61],"used":[66],"networks.":[69],"We":[70],"generate":[71],"low":[72],"latency":[73,152],"high-speed":[75],"streaming":[76],"directly":[79],"from":[80,101,123],"program.":[84],"Our":[85,136],"pipelined":[88],"entirely":[90],"modeled":[91],"using":[92,127],"templated":[93],"\\textttC++":[94,125],"classes.":[95],"pipeline":[97],"layout":[98],"derived":[100],"parser":[103],"graph":[104,115],"that":[105],"corresponds":[106],"P4":[109],"code":[110,120],"after":[111],"series":[113],"transformation":[116],"rounds.":[117],"RTL":[119],"generated":[122],"description":[126],"Xilinx":[128,134,146],"Vivado":[129],"HLS":[130],"synthesized":[132],"Vivado.":[135],"achieves":[138],"\\SI100":[140],"\\giga\\bit/\\second":[141],"rate":[143],"Virtex-7":[147],"FPGA":[148],"while":[149],"reducing":[150],"by":[153,159],"45%":[154],"LUT":[157],"usage":[158],"40%":[160],"compared":[161],"state-of-the-art.":[164]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":11},{"year":2018,"cited_by_count":5}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}