{"id":"https://openalex.org/W2790678706","doi":"https://doi.org/10.1145/3174243.3174264","title":"Dynamically Scheduled High-level Synthesis","display_name":"Dynamically Scheduled High-level Synthesis","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2790678706","doi":"https://doi.org/10.1145/3174243.3174264","mag":"2790678706"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174264","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://infoscience.epfl.ch/handle/20.500.14299/194125","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030147096","display_name":"Lana Josipovi\u0107","orcid":"https://orcid.org/0000-0001-6659-8533"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Lana Josipovi\u0107","raw_affiliation_strings":["\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002705176","display_name":"Radhika Ghosal","orcid":"https://orcid.org/0000-0001-7319-5556"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Radhika Ghosal","raw_affiliation_strings":["\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020575991","display_name":"Paolo Ienne","orcid":"https://orcid.org/0000-0002-6142-7345"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Paolo Ienne","raw_affiliation_strings":["\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030147096"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":9.4695,"has_fulltext":false,"cited_by_count":125,"citation_normalized_percentile":{"value":0.98488548,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"127","last_page":"136"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.9141122102737427},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8689876794815063},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6911729574203491},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6012129187583923},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5479677319526672},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5414725542068481},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5200628638267517},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5088582038879395},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4719877541065216},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4699708819389343},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.4533708095550537},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43189117312431335},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.17998909950256348},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.16563567519187927},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.14755383133888245}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.9141122102737427},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8689876794815063},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6911729574203491},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6012129187583923},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5479677319526672},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5414725542068481},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5200628638267517},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5088582038879395},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4719877541065216},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4699708819389343},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.4533708095550537},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43189117312431335},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17998909950256348},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.16563567519187927},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.14755383133888245},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3174243.3174264","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:299638","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/194125","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"conference proceedings"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:299638","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/194125","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"conference proceedings"},"sustainable_development_goals":[{"score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W37253703","https://openalex.org/W1492601037","https://openalex.org/W1508051931","https://openalex.org/W1513975966","https://openalex.org/W1555915743","https://openalex.org/W1581408681","https://openalex.org/W1843198456","https://openalex.org/W1909835963","https://openalex.org/W1996109622","https://openalex.org/W2012471639","https://openalex.org/W2024390509","https://openalex.org/W2035560780","https://openalex.org/W2039217369","https://openalex.org/W2060569848","https://openalex.org/W2061988908","https://openalex.org/W2071630526","https://openalex.org/W2099129242","https://openalex.org/W2099316112","https://openalex.org/W2103914721","https://openalex.org/W2104869032","https://openalex.org/W2122078405","https://openalex.org/W2122144558","https://openalex.org/W2122553532","https://openalex.org/W2124260068","https://openalex.org/W2129183345","https://openalex.org/W2133156997","https://openalex.org/W2135214818","https://openalex.org/W2157758640","https://openalex.org/W2160566592","https://openalex.org/W2167008350","https://openalex.org/W2253587711","https://openalex.org/W2293666574","https://openalex.org/W2538051842","https://openalex.org/W2542189141","https://openalex.org/W2585062307","https://openalex.org/W2585583922","https://openalex.org/W2757941760","https://openalex.org/W2760331766","https://openalex.org/W2912425543","https://openalex.org/W2913707927","https://openalex.org/W3204019610","https://openalex.org/W4232919122","https://openalex.org/W4239385313","https://openalex.org/W6634898897","https://openalex.org/W6639080219","https://openalex.org/W6691560706"],"related_works":["https://openalex.org/W2145303974","https://openalex.org/W2611818882","https://openalex.org/W4250004442","https://openalex.org/W2703495671","https://openalex.org/W2993981457","https://openalex.org/W2134136106","https://openalex.org/W2171845075","https://openalex.org/W2128998116","https://openalex.org/W1535590766","https://openalex.org/W2126395326"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1,103,181],"(HLS)":[2],"tools":[3,18,182],"almost":[4],"universally":[5],"generate":[6],"statically":[7],"scheduled":[8,65,106],"datapaths.":[9],"Static":[10],"scheduling":[11],"implies":[12],"that":[13,101],"circuits":[14,107],"out":[15],"of":[16,93,104,115,124,191],"HLS":[17,132],"have":[19],"a":[20,116,121,130,137,150],"hard":[21],"time":[22],"exploiting":[23],"parallelism":[24],"in":[25,34,54,76,157,193],"code":[26],"with":[27,31],"potential":[28],"memory":[29],"dependencies,":[30],"control-dependent":[32],"dependencies":[33],"inner":[35],"loops,":[36],"or":[37],"where":[38],"performance":[39,73,141,161],"is":[40,49,108,136,162],"limited":[41],"by":[42,111],"long":[43],"latency":[44],"control":[45],"decisions.":[46],"The":[47],"situation":[48],"essentially":[50],"the":[51,68,71,90,113,134,160,174,189],"same":[52],"as":[53,146],"computer":[55],"architecture":[56],"between":[57,140],"Very-Long":[58],"Instruction":[59],"Word":[60],"(VLIW)":[61],"processors":[62,148],"and":[63,85,142,188],"dynamically":[64,105],"superscalar":[66,147],"processors;":[67],"former":[69],"display":[70],"best":[72],"per":[74],"cost":[75],"highly":[77],"regular":[78],"embedded":[79],"applications,":[80,159],"but":[81],"general":[82],"purpose,":[83],"irregular,":[84],"control-dominated":[86],"computing":[87,192],"tasks":[88],"require":[89],"runtime":[91],"flexibility":[92],"dynamic":[94],"scheduling.":[95],"In":[96],"this":[97],"work,":[98],"we":[99],"show":[100],"high-level":[102,180],"perfectly":[109],"feasible":[110],"describing":[112],"implementation":[114],"prototype":[117],"synthesizer":[118],"which":[119],"generates":[120],"particular":[122],"form":[123],"latency-insensitive":[125],"synchronous":[126],"circuits.":[127],"Compared":[128],"to":[129,154,184],"commercial":[131],"tool,":[133],"result":[135],"different":[138,151],"trade-off":[139,152],"circuit":[143],"complexity,":[144],"much":[145],"represent":[149],"compared":[153],"VLIW":[155],"processors:":[156],"demanding":[158],"very":[163],"significantly":[164],"improved":[165],"at":[166],"an":[167],"affordable":[168],"cost.":[169],"We":[170],"here":[171],"demonstrate":[172],"only":[173],"first":[175],"steps":[176],"towards":[177],"more":[178],"performant":[179],"adapted":[183],"emerging":[185],"FPGA":[186],"applications":[187],"demands":[190],"broader":[194],"application":[195],"domains.":[196]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":21},{"year":2024,"cited_by_count":23},{"year":2023,"cited_by_count":17},{"year":2022,"cited_by_count":23},{"year":2021,"cited_by_count":17},{"year":2020,"cited_by_count":9},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1}],"updated_date":"2026-03-12T08:34:05.389933","created_date":"2025-10-10T00:00:00"}
