{"id":"https://openalex.org/W2788007484","doi":"https://doi.org/10.1145/3174243.3174258","title":"A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform","display_name":"A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2788007484","doi":"https://doi.org/10.1145/3174243.3174258","mag":"2788007484"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174258","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174258","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103274940","display_name":"Duncan J. M. Moss","orcid":"https://orcid.org/0000-0002-1445-6995"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"Duncan J.M Moss","raw_affiliation_strings":["University of Sydney, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"University of Sydney, Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058825852","display_name":"Srivatsan Krishnan","orcid":"https://orcid.org/0000-0002-7148-5389"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srivatsan Krishnan","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084078152","display_name":"Eriko Nurvitadhi","orcid":"https://orcid.org/0000-0002-2347-9590"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eriko Nurvitadhi","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008298406","display_name":"Piotr Ratuszniak","orcid":"https://orcid.org/0000-0001-8792-836X"},"institutions":[{"id":"https://openalex.org/I4210155185","display_name":"Intel (Poland)","ror":"https://ror.org/05bx22c71","country_code":"PL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210155185"]},{"id":"https://openalex.org/I269685040","display_name":"Koszalin University of Technology","ror":"https://ror.org/00x6dk626","country_code":"PL","type":"education","lineage":["https://openalex.org/I269685040"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Piotr Ratuszniak","raw_affiliation_strings":["Intel Corporation & Koszalin University of Technology, Gdansk, Poland"],"affiliations":[{"raw_affiliation_string":"Intel Corporation & Koszalin University of Technology, Gdansk, Poland","institution_ids":["https://openalex.org/I269685040","https://openalex.org/I4210155185"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066723059","display_name":"Christopher N. Johnson","orcid":"https://orcid.org/0000-0002-9719-3771"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Johnson","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004251886","display_name":"Jaewoong Sim","orcid":"https://orcid.org/0000-0002-0403-9928"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaewoong Sim","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101912070","display_name":"Asit Mishra","orcid":"https://orcid.org/0000-0001-6489-6895"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Asit Mishra","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110600508","display_name":"Debbie Marr","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Debbie Marr","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085936979","display_name":"Suchit Subhaschandra","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Suchit Subhaschandra","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107994859","display_name":"Philip H. W. Leong","orcid":"https://orcid.org/0000-0002-3923-3499"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Philip H.W. Leong","raw_affiliation_strings":["University of Sydney, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"University of Sydney, Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5103274940"],"corresponding_institution_ids":["https://openalex.org/I129604602"],"apc_list":null,"apc_paid":null,"fwci":14.6432,"has_fulltext":false,"cited_by_count":82,"citation_normalized_percentile":{"value":0.99425568,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"107","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.849083423614502},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.6753073930740356},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6659428477287292},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.5783548951148987},{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.5344694256782532},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.5096895694732666},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5084906816482544},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.48539862036705017},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4709666073322296},{"id":"https://openalex.org/keywords/single-precision-floating-point-format","display_name":"Single-precision floating-point format","score":0.4690711200237274},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.42825838923454285},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34000521898269653},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2900363802909851},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22946912050247192}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.849083423614502},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.6753073930740356},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6659428477287292},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.5783548951148987},{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.5344694256782532},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.5096895694732666},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5084906816482544},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.48539862036705017},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4709666073322296},{"id":"https://openalex.org/C133095886","wikidata":"https://www.wikidata.org/wiki/Q1307173","display_name":"Single-precision floating-point format","level":3,"score":0.4690711200237274},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.42825838923454285},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34000521898269653},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2900363802909851},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22946912050247192},{"id":"https://openalex.org/C24890656","wikidata":"https://www.wikidata.org/wiki/Q82811","display_name":"Acoustics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3174243.3174258","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174258","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334704","display_name":"Australian Research Council","ror":"https://ror.org/05mmh0f86"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1667652561","https://openalex.org/W1686810756","https://openalex.org/W1902934009","https://openalex.org/W2117539524","https://openalex.org/W2149381887","https://openalex.org/W2194775991","https://openalex.org/W2284104857","https://openalex.org/W2300242332","https://openalex.org/W2319920447","https://openalex.org/W2405102949","https://openalex.org/W2565125333","https://openalex.org/W2574797063","https://openalex.org/W2583383421","https://openalex.org/W2583831344","https://openalex.org/W2584616277","https://openalex.org/W2585560244","https://openalex.org/W2587865853","https://openalex.org/W2591922920","https://openalex.org/W2606722458","https://openalex.org/W2612264667","https://openalex.org/W2613514830","https://openalex.org/W2618530766","https://openalex.org/W2727238169","https://openalex.org/W2764337919","https://openalex.org/W2949245006","https://openalex.org/W2951460453","https://openalex.org/W2952197171","https://openalex.org/W2953212265","https://openalex.org/W3102169921"],"related_works":["https://openalex.org/W1974923383","https://openalex.org/W2475524688","https://openalex.org/W2739740241","https://openalex.org/W2085105049","https://openalex.org/W2526069705","https://openalex.org/W2024016913","https://openalex.org/W2265064666","https://openalex.org/W2156524298","https://openalex.org/W1953299766","https://openalex.org/W2550374317"],"abstract_inverted_index":{"General":[0],"Matrix":[1,3],"to":[2],"multiplication":[4,36],"(GEMM)":[5],"is":[6],"the":[7,39,104],"cornerstone":[8],"for":[9,38,47,76,99,150],"a":[10,33,70,86],"wide":[11],"gamut":[12],"of":[13,66,103],"applications":[14],"in":[15],"high":[16],"performance":[17],"computing":[18,21],"(HPC),":[19],"scientific":[20],"(SC)":[22],"and":[23,54,64,79,84,96,112,116,134,138,145],"more":[24,146],"recently,":[25],"deep":[26,118,151],"learning.":[27],"In":[28],"this":[29],"work,":[30],"we":[31],"present":[32],"customizable":[34,88],"matrix":[35],"framework":[37,59,123],"Intel":[40],"HARPv2":[41],"CPU+FPGA":[42],"platform":[43],"that":[44],"includes":[45],"support":[46],"both":[48,94],"traditional":[49],"single":[50,126],"precision":[51,56,109,127],"floating":[52,128],"point":[53,129],"reduced":[55],"workloads.":[57],"Our":[58],"supports":[60,125],"arbitrary":[61],"size":[62,114],"GEMMs":[63],"consists":[65],"two":[67],"parts:":[68],"(1)":[69],"simple":[71],"application":[72],"programming":[73],"interface":[74],"(API)":[75],"easy":[77],"configuration":[78],"integration":[80],"into":[81],"existing":[82],"software":[83],"(2)":[85],"highly":[87],"hardware":[89,105],"template.":[90],"The":[91,122],"API":[92],"provides":[93],"compile":[95],"runtime":[97],"options":[98],"controlling":[100],"key":[101],"aspects":[102],"template":[106],"including":[107],"dynamic":[108],"switching;":[110],"interleaving":[111],"block":[113],"control;":[115],"fused":[117],"learning":[119,152],"specific":[120],"operations.":[121],"currently":[124],"(FP32),":[130],"16,":[131],"8,":[132],"4":[133],"2":[135],"bit":[136],"Integer":[137],"Fixed":[139],"Point":[140],"(INT16,":[141],"INT8,":[142],"INT4,":[143],"INT2)":[144],"exotic":[147],"data":[148],"types":[149],"workloads:":[153],"INT16xTernary,":[154],"INT8xTernary,":[155],"BinaryxBinary.":[156]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":13},{"year":2019,"cited_by_count":21},{"year":2018,"cited_by_count":14}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}