{"id":"https://openalex.org/W2788726558","doi":"https://doi.org/10.1145/3174243.3174247","title":"ADAM","display_name":"ADAM","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2788726558","doi":"https://doi.org/10.1145/3174243.3174247","mag":"2788726558"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174247","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174247","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056411319","display_name":"Ho-Cheung Ng","orcid":"https://orcid.org/0000-0002-5171-1318"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Ho-Cheung Ng","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101818400","display_name":"Shuanglong Liu","orcid":"https://orcid.org/0000-0002-1513-1981"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Shuanglong Liu","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5056411319"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":1.1777,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.79454267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"189","last_page":"198"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8317214250564575},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7591300010681152},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6368640661239624},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5752317309379578},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5626827478408813},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5308671593666077},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4804946184158325},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.4267657399177551},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34179210662841797},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3405325412750244},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3360271453857422},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.298961877822876},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22023072838783264},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.21920201182365417},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1395069658756256},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11778879165649414}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8317214250564575},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7591300010681152},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6368640661239624},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5752317309379578},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5626827478408813},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5308671593666077},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4804946184158325},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.4267657399177551},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34179210662841797},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3405325412750244},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3360271453857422},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.298961877822876},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22023072838783264},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.21920201182365417},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1395069658756256},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11778879165649414},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3174243.3174247","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174247","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5}],"awards":[{"id":"https://openalex.org/G2784140359","display_name":"Application Customisation: Enhancing Design Quality and Developer Productivity","funder_award_id":"EP/P010040/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5201431165","display_name":"EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems","funder_award_id":"EP/L016796/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5248561189","display_name":"Event-based parallel computing - partially ordered event-triggered systems (POETS)","funder_award_id":"EP/N031768/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5549522161","display_name":null,"funder_award_id":"P/L00058X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G600182179","display_name":null,"funder_award_id":"EP/L00058X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G6653872853","display_name":null,"funder_award_id":"EP/L016","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G6968114954","display_name":"Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems","funder_award_id":"EP/L00058X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G7493804148","display_name":null,"funder_award_id":"EP/N031768/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G774180880","display_name":null,"funder_award_id":"EP/P010040/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8719353587","display_name":null,"funder_award_id":"EP/P0","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":49,"referenced_works":["https://openalex.org/W200676892","https://openalex.org/W347636100","https://openalex.org/W1551696500","https://openalex.org/W1961025862","https://openalex.org/W1970340536","https://openalex.org/W1972387588","https://openalex.org/W1975465680","https://openalex.org/W1983394510","https://openalex.org/W1985681048","https://openalex.org/W1994285181","https://openalex.org/W2005602803","https://openalex.org/W2008781896","https://openalex.org/W2023844339","https://openalex.org/W2047143252","https://openalex.org/W2052237150","https://openalex.org/W2052930524","https://openalex.org/W2062435236","https://openalex.org/W2064449682","https://openalex.org/W2064997970","https://openalex.org/W2069187850","https://openalex.org/W2069523538","https://openalex.org/W2081201959","https://openalex.org/W2098133383","https://openalex.org/W2099132653","https://openalex.org/W2105917387","https://openalex.org/W2107350738","https://openalex.org/W2117654656","https://openalex.org/W2126106175","https://openalex.org/W2126594417","https://openalex.org/W2138383740","https://openalex.org/W2139817798","https://openalex.org/W2150022482","https://openalex.org/W2150843905","https://openalex.org/W2153331583","https://openalex.org/W2244473793","https://openalex.org/W2279391168","https://openalex.org/W2284768363","https://openalex.org/W2472489786","https://openalex.org/W2475663704","https://openalex.org/W2524556139","https://openalex.org/W2554510265","https://openalex.org/W2575834586","https://openalex.org/W2597728377","https://openalex.org/W2761496944","https://openalex.org/W2950784896","https://openalex.org/W4236433846","https://openalex.org/W4237406999","https://openalex.org/W4241916159","https://openalex.org/W4388215268"],"related_works":["https://openalex.org/W2293118914","https://openalex.org/W2998381397","https://openalex.org/W4236419692","https://openalex.org/W3167919718","https://openalex.org/W2999668243","https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W3116537445","https://openalex.org/W2390885485","https://openalex.org/W4312121077"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"ADAM,":[3],"an":[4],"approach":[5],"for":[6,77,119],"merging":[7],"multiple":[8,18],"FPGA":[9],"designs":[10,99],"into":[11],"a":[12,25,46,68,103],"single":[13,26],"hardware":[14],"design,":[15],"so":[16],"that":[17,126],"place-and-route":[19],"tasks":[20],"can":[21,128],"be":[22],"replaced":[23],"by":[24,132],"task":[27],"to":[28,58,93,113,142,154],"speed":[29],"up":[30],"functional":[31],"evaluation":[32],"of":[33,61,96,106,111,160],"designs,":[34],"especially":[35],"during":[36],"the":[37,64,89,97,115,120,143,146,158],"development":[38],"process.":[39],"ADAM":[40,127],"has":[41],"three":[42],"key":[43],"elements.":[44],"First,":[45],"novel":[47],"approximate":[48],"maximum":[49],"common":[50,73],"subgraph":[51,74],"detection":[52,75],"algorithm":[53,76],"with":[54],"linear":[55],"time":[56,108,131,148],"complexity":[57],"maximize":[59],"sharing":[60],"resources":[62],"in":[63,157],"merged":[65],"design.":[66],"Second,":[67],"prototype":[69],"tool":[70,85],"implementing":[71],"this":[72,84],"dataflow":[78],"graphs":[79],"derived":[80],"from":[81,151],"Verilog":[82],"designs;":[83],"would":[86],"also":[87],"generate":[88],"appropriate":[90],"control":[91],"circuits":[92],"enable":[94],"selection":[95],"original":[98],"at":[100],"runtime.":[101],"Third,":[102],"comprehensive":[104],"analysis":[105],"compilation":[107,130,147],"versus":[109],"degree":[110],"similarity":[112],"identify":[114],"optimized":[116],"user":[117],"parameters":[118],"proposed":[121],"approach.":[122],"Experimental":[123],"results":[124],"show":[125],"reduce":[129],"around":[133],"5":[134],"times":[135],"when":[136],"each":[137],"design":[138],"is":[139,149],"95%":[140],"similar":[141],"others,":[144],"and":[145],"reduced":[150],"1":[152],"hour":[153],"10":[155],"minutes":[156],"case":[159],"binomial":[161],"filters.":[162]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2018-03-06T00:00:00"}
