{"id":"https://openalex.org/W2788825665","doi":"https://doi.org/10.1145/3174243.3174244","title":"Liquid Silicon","display_name":"Liquid Silicon","publication_year":2018,"publication_date":"2018-02-15","ids":{"openalex":"https://openalex.org/W2788825665","doi":"https://doi.org/10.1145/3174243.3174244","mag":"2788825665"},"language":"en","primary_location":{"id":"doi:10.1145/3174243.3174244","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076566818","display_name":"Yue Zha","orcid":"https://orcid.org/0000-0003-1111-7178"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yue Zha","raw_affiliation_strings":["University of Wisconsin Madison, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"University of Wisconsin Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100626667","display_name":"Jing Li","orcid":"https://orcid.org/0000-0001-5139-938X"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jing Li","raw_affiliation_strings":["University of Wisconsin Madison, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"University of Wisconsin Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5076566818"],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":0.9107,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.75430927,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"51","last_page":"60"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7043321132659912},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6898825168609619},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.63836270570755},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5394163727760315},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4715704321861267},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.44938579201698303},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.448660284280777},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.44855931401252747},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4350094795227051},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4265940487384796},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32596755027770996},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.24726605415344238},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.21652036905288696},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.21579614281654358},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13327357172966003}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7043321132659912},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6898825168609619},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.63836270570755},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5394163727760315},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4715704321861267},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.44938579201698303},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.448660284280777},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.44855931401252747},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4350094795227051},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4265940487384796},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32596755027770996},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.24726605415344238},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.21652036905288696},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.21579614281654358},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13327357172966003},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3174243.3174244","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3174243.3174244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7400000095367432,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1964675090","https://openalex.org/W1966570140","https://openalex.org/W1969908552","https://openalex.org/W1971000062","https://openalex.org/W1977773606","https://openalex.org/W1982565841","https://openalex.org/W1993728494","https://openalex.org/W1996635038","https://openalex.org/W2004823737","https://openalex.org/W2005602803","https://openalex.org/W2022698427","https://openalex.org/W2027342132","https://openalex.org/W2028061426","https://openalex.org/W2030949838","https://openalex.org/W2036899386","https://openalex.org/W2076613578","https://openalex.org/W2086709250","https://openalex.org/W2098730617","https://openalex.org/W2100955320","https://openalex.org/W2114965603","https://openalex.org/W2118995854","https://openalex.org/W2125469204","https://openalex.org/W2139399616","https://openalex.org/W2139924560","https://openalex.org/W2146437820","https://openalex.org/W2147004330","https://openalex.org/W2149380925","https://openalex.org/W2150313118","https://openalex.org/W2166637744","https://openalex.org/W2168493238","https://openalex.org/W2170510975","https://openalex.org/W2171768221","https://openalex.org/W2178102281","https://openalex.org/W2183928302","https://openalex.org/W2289106931","https://openalex.org/W2295615355","https://openalex.org/W2331783522","https://openalex.org/W2536878608","https://openalex.org/W2585774018","https://openalex.org/W3140396777","https://openalex.org/W4214686615","https://openalex.org/W4239323126","https://openalex.org/W4239721110"],"related_works":["https://openalex.org/W3180803030","https://openalex.org/W2993507867","https://openalex.org/W3025845664","https://openalex.org/W2148264254","https://openalex.org/W1970751325","https://openalex.org/W2170925376","https://openalex.org/W2168550483","https://openalex.org/W4248370144","https://openalex.org/W2105031241","https://openalex.org/W2768900401"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,29,33,48],"data-centric":[4],"reconfigurable":[5],"architecture,":[6],"namely":[7],"Liquid":[8,25,167],"Silicon,":[9],"enabled":[10],"by":[11],"emerging":[12,148],"non-volatile":[13],"memory,":[14],"i.e.,":[15,100],"RRAM.":[16],"Compared":[17],"to":[18,62,71,85,110],"the":[19,72,95],"heterogeneous":[20],"architecture":[21,31,92],"of":[22,37,50,97,170],"commercial":[23,98],"FPGAs,":[24],"Silicon":[26,168],"is":[27],"inherently":[28],"homogeneous":[30],"comprising":[32],"two-dimensional":[34],"(2D)":[35],"array":[36],"identical":[38],"'tiles'.":[39],"Each":[40],"tile":[41],"can":[42],"be":[43],"configured":[44],"into":[45],"one":[46],"or":[47],"combination":[49],"four":[51],"modes:":[52],"TCAM,":[53],"logic,":[54],"interconnect,":[55],"and":[56,126,130,147,157],"memory.":[57],"Such":[58],"flexibility":[59],"allows":[60],"users":[61],"partition":[63],"resources":[64],"based":[65],"on":[66,142],"applications?":[67],"needs,":[68],"in":[69,81,118,160],"contrast":[70],"fixed":[73],"hardware":[74],"design":[75],"using":[76],"dedicated":[77],"hard":[78],"IP":[79],"blocks":[80],"FPGAs.":[82,111,171],"In":[83],"addition":[84],"better":[86,131],"resource":[87],"usage,":[88],"its":[89,113,135],"'memory":[90],"friendly'":[91],"effectively":[93],"addresses":[94],"limitations":[96],"FPGAs":[99],"scarce":[101],"on-chip":[102],"memory":[103],"resources,":[104],"making":[105],"it":[106],"an":[107],"effective":[108],"complement":[109],"Moreover,":[112],"coarse-grained":[114],"logic":[115,120],"implementation":[116],"results":[117],"shallower":[119],"depth,":[121],"less":[122],"inter-tile":[123],"routing":[124],"overhead,":[125],"thus":[127],"smaller":[128],"area":[129,153],"performance,":[132],"compared":[133],"with":[134],"FPGA":[136],"counterpart.":[137],"Our":[138],"study":[139],"shows":[140],"that,":[141],"average,":[143],"for":[144],"both":[145],"traditional":[146],"applications,":[149],"we":[150],"achieve":[151],"62%":[152],"reduction,":[154],"27%":[155],"speedup":[156],"31%":[158],"improvement":[159],"energy":[161],"efficiency":[162],"when":[163],"mapping":[164],"applications":[165],"onto":[166],"instead":[169]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3}],"updated_date":"2026-03-06T13:50:29.536080","created_date":"2018-03-06T00:00:00"}
