{"id":"https://openalex.org/W4300801551","doi":"https://doi.org/10.1145/3139540","title":"Proceedings of the 10th International Workshop on Network on Chip Architectures","display_name":"Proceedings of the 10th International Workshop on Network on Chip Architectures","publication_year":2017,"publication_date":"2017-10-14","ids":{"openalex":"https://openalex.org/W4300801551","doi":"https://doi.org/10.1145/3139540"},"language":"en","primary_location":{"id":"doi:10.1145/3139540","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3139540","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"proceedings"},"type":"paratext","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":true,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9878000020980835,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.8154797554016113},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7340837717056274},{"id":"https://openalex.org/keywords/hol","display_name":"HOL","score":0.6965800523757935},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6910208463668823},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.6261230707168579},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5424670577049255},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5362159013748169},{"id":"https://openalex.org/keywords/blocking","display_name":"Blocking (statistics)","score":0.5348675847053528},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4834069311618805},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.45211657881736755},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.43554747104644775},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.41756671667099},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4170669913291931},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35570716857910156},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3454534709453583},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1545484960079193},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.14661303162574768},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12311673164367676}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.8154797554016113},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7340837717056274},{"id":"https://openalex.org/C17435882","wikidata":"https://www.wikidata.org/wiki/Q17030435","display_name":"HOL","level":2,"score":0.6965800523757935},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6910208463668823},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.6261230707168579},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5424670577049255},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5362159013748169},{"id":"https://openalex.org/C144745244","wikidata":"https://www.wikidata.org/wiki/Q4927286","display_name":"Blocking (statistics)","level":2,"score":0.5348675847053528},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4834069311618805},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.45211657881736755},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.43554747104644775},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.41756671667099},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4170669913291931},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35570716857910156},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3454534709453583},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1545484960079193},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.14661303162574768},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12311673164367676},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3139540","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3139540","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"proceedings"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2751820975","https://openalex.org/W2388672758","https://openalex.org/W2135981148","https://openalex.org/W2175646906","https://openalex.org/W2754086592","https://openalex.org/W1969623596","https://openalex.org/W2144357574","https://openalex.org/W2065289416","https://openalex.org/W3198758847","https://openalex.org/W4230458348"],"abstract_inverted_index":{"Virtual":[0],"Channels":[1],"(VCs)":[2],"are":[3],"a":[4],"fundamental":[5],"design":[6],"feature":[7],"across":[8],"networks,":[9],"both":[10],"on-chip":[11],"and":[12,22,34],"off-chip.":[13],"They":[14],"provide":[15],"two":[16],"key":[17],"benefits":[18],"-":[19],"deadlock":[20],"avoidance":[21],"head-of-line":[23],"(HoL)":[24],"blocking":[25],"mitigation.":[26],"However,":[27],"VCs":[28],"increase":[29],"the":[30],"router":[31],"critical":[32],"path,":[33],"add":[35],"...":[36]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
