{"id":"https://openalex.org/W2761739353","doi":"https://doi.org/10.1145/3132402.3132437","title":"Memory equalizer for lateral management of heterogeneous memory","display_name":"Memory equalizer for lateral management of heterogeneous memory","publication_year":2017,"publication_date":"2017-10-02","ids":{"openalex":"https://openalex.org/W2761739353","doi":"https://doi.org/10.1145/3132402.3132437","mag":"2761739353"},"language":"en","primary_location":{"id":"doi:10.1145/3132402.3132437","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3132402.3132437","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102871859","display_name":"Chencheng Ye","orcid":"https://orcid.org/0000-0003-3432-855X"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chencheng Ye","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, Hubei, China"],"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, Hubei, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002777604","display_name":"Chen Ding","orcid":"https://orcid.org/0000-0003-4968-6659"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chen Ding","raw_affiliation_strings":["University of Rochester"],"affiliations":[{"raw_affiliation_string":"University of Rochester","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022262922","display_name":"Hai Jin","orcid":"https://orcid.org/0000-0002-3934-7605"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hai Jin","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, Hubei, China"],"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, Hubei, China","institution_ids":["https://openalex.org/I47720641"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5102871859"],"corresponding_institution_ids":["https://openalex.org/I47720641"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14751756,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"239","last_page":"248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7872828245162964},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.6771705150604248},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5694736838340759},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5457172393798828},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5447030067443848},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5429016351699829},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.5113117694854736},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.5036172270774841},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.47807788848876953},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4325612187385559},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.41925501823425293},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.41565006971359253},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3804417550563812},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2119770348072052},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11193069815635681},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10174483060836792},{"id":"https://openalex.org/keywords/phase-change","display_name":"Phase change","score":0.08886191248893738}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7872828245162964},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.6771705150604248},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5694736838340759},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5457172393798828},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5447030067443848},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5429016351699829},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.5113117694854736},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.5036172270774841},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.47807788848876953},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4325612187385559},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.41925501823425293},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.41565006971359253},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3804417550563812},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2119770348072052},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11193069815635681},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10174483060836792},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.08886191248893738},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3132402.3132437","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3132402.3132437","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6734354105","display_name":null,"funder_award_id":"CCF-1717877, CCF-1629376, CNS-1319617","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W288065879","https://openalex.org/W307918303","https://openalex.org/W1487184349","https://openalex.org/W1931046221","https://openalex.org/W1967474856","https://openalex.org/W1969835518","https://openalex.org/W1985229168","https://openalex.org/W2043557409","https://openalex.org/W2052040062","https://openalex.org/W2062296288","https://openalex.org/W2087946700","https://openalex.org/W2088257029","https://openalex.org/W2091907331","https://openalex.org/W2142098074","https://openalex.org/W2144941482","https://openalex.org/W2168900306","https://openalex.org/W2169875292","https://openalex.org/W2171519206","https://openalex.org/W2218592960","https://openalex.org/W2293221651","https://openalex.org/W2294352052","https://openalex.org/W2340076492","https://openalex.org/W2346051120","https://openalex.org/W2414237234","https://openalex.org/W2536162499","https://openalex.org/W2554695184","https://openalex.org/W2609137082","https://openalex.org/W2740361432","https://openalex.org/W2970089458","https://openalex.org/W4235336266","https://openalex.org/W4237211384"],"related_works":["https://openalex.org/W3048967625","https://openalex.org/W4243618206","https://openalex.org/W2056436264","https://openalex.org/W4248614727","https://openalex.org/W2138825797","https://openalex.org/W2296275612","https://openalex.org/W1575240748","https://openalex.org/W2057867585","https://openalex.org/W2612506697","https://openalex.org/W2140386982"],"abstract_inverted_index":{"Modern":[0],"computers":[1],"increasingly":[2],"use":[3],"more":[4,18],"types":[5],"of":[6],"memory":[7,11,24],"such":[8],"as":[9],"phase-change":[10],"and":[12,20],"high-bandwidth":[13],"memory.":[14],"Consequently,":[15],"it":[16],"is":[17],"complex":[19],"difficult":[21],"to":[22],"manage":[23],"effectively.":[25]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
