{"id":"https://openalex.org/W2764172931","doi":"https://doi.org/10.1145/3132402.3132426","title":"Lightweight SIMT core designs for intelligent 3D stacked DRAM","display_name":"Lightweight SIMT core designs for intelligent 3D stacked DRAM","publication_year":2017,"publication_date":"2017-10-02","ids":{"openalex":"https://openalex.org/W2764172931","doi":"https://doi.org/10.1145/3132402.3132426","mag":"2764172931"},"language":"en","primary_location":{"id":"doi:10.1145/3132402.3132426","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3132402.3132426","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012725183","display_name":"Chad Kersey","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chad D. Kersey","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000822269","display_name":"Hyesoon Kim","orcid":"https://orcid.org/0000-0002-6061-7825"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyesoon Kim","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111855694","display_name":"Sudhakar Yalamanchili","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar Yalamanchili","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5012725183"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.6759,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.69746398,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"49","last_page":"59"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7651381492614746},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.645226001739502},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5847156047821045},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5571529269218445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4775170385837555},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.46708035469055176},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4479946494102478},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4380648136138916},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.424820214509964},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3663887083530426},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35273855924606323},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3268299698829651}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7651381492614746},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.645226001739502},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5847156047821045},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5571529269218445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4775170385837555},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.46708035469055176},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4479946494102478},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4380648136138916},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.424820214509964},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3663887083530426},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35273855924606323},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3268299698829651},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3132402.3132426","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3132402.3132426","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G8305552798","display_name":null,"funder_award_id":"CCF-1533767","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1858644877","https://openalex.org/W1975237352","https://openalex.org/W1981220134","https://openalex.org/W1981943579","https://openalex.org/W1983394510","https://openalex.org/W1985291160","https://openalex.org/W1987163471","https://openalex.org/W2054095206","https://openalex.org/W2082695854","https://openalex.org/W2112547256","https://openalex.org/W2124969960","https://openalex.org/W2155509874","https://openalex.org/W2162385899","https://openalex.org/W2177565047","https://openalex.org/W2335240678","https://openalex.org/W2409197925","https://openalex.org/W2413156605","https://openalex.org/W2515406844","https://openalex.org/W2517869808","https://openalex.org/W2518511512","https://openalex.org/W2557515111","https://openalex.org/W2583135230","https://openalex.org/W4239722617","https://openalex.org/W4245440340","https://openalex.org/W4250370106"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W4401568740","https://openalex.org/W2098207691","https://openalex.org/W3148568549","https://openalex.org/W1648516568","https://openalex.org/W361036515","https://openalex.org/W4392590355","https://openalex.org/W2269474412","https://openalex.org/W4386903460","https://openalex.org/W4211178602"],"abstract_inverted_index":{"In":[0,63],"this":[1,64],"work":[2],"we":[3],"present":[4,185],"an":[5,56,175],"analysis":[6],"of":[7,29,41,58,75,96,140,149,158,167,169,177,179],"the":[8,27,34,39,50,77,109,124,138,147,165,183],"Harmonica":[9,30,71,97,161],"stream":[10],"multiprocessor,":[11],"a":[12,42,46,67,102,113,118,172,187],"light-weight,":[13],"parameterized,":[14],"open-source":[15],"single-instruction-multiple-thread":[16],"(SIMT)":[17],"core":[18],"designed":[19],"for":[20,105,135,174],"integration":[21],"within":[22,108],"3D-stacked":[23],"DRAM.":[24],"We":[25],"evaluate":[26],"range":[28],"designs":[31],"afforded":[32],"by":[33],"architecture's":[35],"parameter":[36],"space":[37],"in":[38,186],"role":[40],"vault-level":[43],"accelerator,":[44],"augmenting":[45],"design":[47,115,127],"similar":[48],"to":[49,88,129,146],"Micron":[51],"Hybrid":[52],"Memory":[53],"Cube":[54],"into":[55],"array":[57],"compact":[59],"accelerated":[60],"DRAM":[61],"channels.":[62],"role,":[65],"with":[66],"small":[68,79],"SRAM":[69],"cache,":[70],"cores":[72,162],"are":[73,98],"capable":[74],"providing":[76,101,133],"requisite":[78],"footprint,":[80],"energy":[81],"efficiency,":[82],"latency":[83,184],"tolerance,":[84],"and":[85,94,112,132,142],"bandwidth":[86,180],"demand":[87,173],"perform":[89],"well.":[90],"The":[91],"instruction":[92],"set":[93],"microarchitecture":[95],"both":[99],"novel,":[100],"lightweight":[103],"interface":[104],"thread":[106],"creation":[107],"SIMT":[110],"model":[111],"simple":[114],"that":[116],"issues":[117],"single":[119],"warp":[120,145],"per":[121,144,153],"cycle,":[122],"simplifying":[123],"register":[125],"file":[126],"compared":[128],"high-performance":[130],"GPUs,":[131],"parameters":[134],"attributes":[136],"from":[137],"number":[139,148],"warps":[141],"threads":[143],"general":[150],"purpose":[151],"registers":[152],"thread.":[154],"For":[155],"our":[156],"suite":[157],"analytics-oriented":[159],"benchmarks,":[160],"consuming":[163],"on":[164],"order":[166],"100mW":[168],"power":[170],"maintain":[171],"average":[176],"12GB/s":[178],"while":[181],"tolerating":[182],"DRAM-based":[188],"memory":[189],"system.":[190]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":6},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}