{"id":"https://openalex.org/W2755574246","doi":"https://doi.org/10.1145/3130218.3132339","title":"Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable","display_name":"Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable","publication_year":2017,"publication_date":"2017-09-20","ids":{"openalex":"https://openalex.org/W2755574246","doi":"https://doi.org/10.1145/3130218.3132339","mag":"2755574246"},"language":"en","primary_location":{"id":"doi:10.1145/3130218.3132339","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3130218.3132339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026355063","display_name":"Ahmed Hemani","orcid":"https://orcid.org/0000-0003-0565-9376"},"institutions":[{"id":"https://openalex.org/I4210160701","display_name":"Kista Photonics Research Center","ror":"https://ror.org/05j59av97","country_code":"SE","type":"facility","lineage":["https://openalex.org/I4210160701"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Ahmed Hemani","raw_affiliation_strings":["Dept. of Electronics, School of ICT, KTH, Kista, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, School of ICT, KTH, Kista, Sweden","institution_ids":["https://openalex.org/I4210160701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110525979","display_name":"Syed Mohammed Asad Hassan Jafri","orcid":null},"institutions":[{"id":"https://openalex.org/I4210160701","display_name":"Kista Photonics Research Center","ror":"https://ror.org/05j59av97","country_code":"SE","type":"facility","lineage":["https://openalex.org/I4210160701"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Syed Mohammed Asad Hassan Jafri","raw_affiliation_strings":["Dept. of Electronics, School of ICT, KTH, Kista, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, School of ICT, KTH, Kista, Sweden","institution_ids":["https://openalex.org/I4210160701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047591737","display_name":"Shayesteh Masoumian","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Shayesteh Masoumian","raw_affiliation_strings":["School of Electrical &amp; Computer Engineering, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical &amp; Computer Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3182,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.83694438,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7355257272720337},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6616408824920654},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6477194428443909},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6322064995765686},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5894871950149536},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5736275315284729},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5677524209022522},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5339545011520386},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5300588011741638},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.5085185766220093},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5009286403656006},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4764312207698822},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4658181667327881},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45454925298690796},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4500565230846405},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4424165189266205},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.43426400423049927},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4156649112701416},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.372591495513916},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36869800090789795},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.29088684916496277},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2528817653656006},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2138271927833557},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.19289901852607727},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11728420853614807},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09390726685523987},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09217631816864014}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7355257272720337},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6616408824920654},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6477194428443909},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6322064995765686},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5894871950149536},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5736275315284729},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5677524209022522},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5339545011520386},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5300588011741638},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.5085185766220093},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5009286403656006},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4764312207698822},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4658181667327881},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45454925298690796},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4500565230846405},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4424165189266205},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.43426400423049927},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4156649112701416},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.372591495513916},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36869800090789795},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.29088684916496277},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2528817653656006},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2138271927833557},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.19289901852607727},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11728420853614807},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09390726685523987},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09217631816864014},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3130218.3132339","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3130218.3132339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1513138710","https://openalex.org/W1561157983","https://openalex.org/W1575535798","https://openalex.org/W1965359258","https://openalex.org/W1978432500","https://openalex.org/W1985856855","https://openalex.org/W2020380328","https://openalex.org/W2026412731","https://openalex.org/W2039920015","https://openalex.org/W2066139250","https://openalex.org/W2084529981","https://openalex.org/W2097303307","https://openalex.org/W2117385926","https://openalex.org/W2121082877","https://openalex.org/W2122546367","https://openalex.org/W2123184444","https://openalex.org/W2134673133","https://openalex.org/W2143220063","https://openalex.org/W2144175376","https://openalex.org/W2160642395","https://openalex.org/W2163953032","https://openalex.org/W2167548482","https://openalex.org/W2187968236","https://openalex.org/W2564337795","https://openalex.org/W2607477256","https://openalex.org/W2626211758","https://openalex.org/W2724934780","https://openalex.org/W2736984141","https://openalex.org/W2751826671","https://openalex.org/W4212990656","https://openalex.org/W4229976825"],"related_works":["https://openalex.org/W2576551918","https://openalex.org/W2337636225","https://openalex.org/W1572747186","https://openalex.org/W162881505","https://openalex.org/W2783693002","https://openalex.org/W2119373721","https://openalex.org/W4294611724","https://openalex.org/W2922751745","https://openalex.org/W2028951941","https://openalex.org/W2047695881"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4,214],"a":[5,121],"novel":[6],"synchoros":[7,49],"VLSI":[8,57],"design":[9,29,58,124,150],"scheme":[10],"that":[11,126],"discretizes":[12],"space":[13],"uniformly.":[14],"Synchoros":[15],"derives":[16],"from":[17],"the":[18,27,86,90,117,160,169,190,224,232],"Greek":[19],"word":[20],"ch\u00f3ros":[21],"for":[22],"space.":[23],"We":[24,158,212],"propose":[25],"raising":[26],"physical":[28,70,149],"abstraction":[30],"to":[31,53,98,129,141,175,192,205,222,230],"register":[32],"transfer":[33],"level":[34],"by":[35,60,76],"using":[36],"coarse":[37],"grain":[38],"reconfigurable":[39],"building":[40],"blocks":[41,46,73,88],"called":[42,116],"SiLago":[43,45,72,87,118],"blocks.":[44],"are":[47,51,74],"hardened,":[48],"and":[50,63,69,82,89,110,146,163,165,182],"used":[52],"create":[54,99],"arbitrarily":[55],"complex":[56],"instances":[59],"abutting":[61],"them":[62],"not":[64],"requiring":[65],"any":[66],"further":[67],"logic":[68],"syntheses.":[71],"interconnected":[75],"two":[77,91,177],"levels":[78,92],"of":[79,93,132,156,227],"NOCs,":[80,94],"regional":[81],"global.":[83],"By":[84],"configuring":[85],"it":[95],"is":[96,202],"possible":[97],"implementation":[100],"alternatives":[101],"whose":[102],"cost":[103,226],"metrics":[104],"can":[105],"be":[106,142],"evaluated":[107],"with":[108,207],"agility":[109],"post":[111],"layout":[112],"accuracy.":[113],"This":[114],"framework,":[115],"framework":[119],"includes":[120],"synthesis":[122,161,187],"based":[123,173],"flow":[125],"allows":[127],"end":[128,130],"automation":[131],"multi-million":[133],"gate":[134],"functionality":[135],"modeled":[136],"as":[137],"SDF":[138],"in":[139,151,180,186],"Simulink":[140],"transformed":[143],"into":[144],"timing":[145],"DRC":[147],"clean":[148],"minutes,":[152],"while":[153,188],"exploring":[154],"100s":[155],"solutions.":[157],"benchmark":[159],"efficiency,":[162],"silicon":[164],"computational":[166],"efficiencies":[167],"against":[168],"conventional":[170],"standard":[171],"cell":[172],"tooling":[174],"show":[176],"orders":[178,184],"improvement":[179,185],"accuracy":[181],"three":[183],"eliminating":[189,223],"need":[191],"verify":[193],"at":[194],"lower":[195,231],"abstractions":[196],"like":[197],"RTL.":[198],"The":[199],"proposed":[200],"solution":[201],"being":[203],"extended":[204],"deal":[206],"system-level":[208],"non-compile":[209],"time":[210],"functionalities.":[211],"also":[213,220],"arguments":[215],"on":[216],"how":[217],"synchoricity":[218],"could":[219],"contribute":[221],"engineering":[225],"designing":[228],"masks":[229],"manufacturing":[233],"cost.":[234]},"counts_by_year":[{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
