{"id":"https://openalex.org/W2754086592","doi":"https://doi.org/10.1145/3130218.3130238","title":"System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip","display_name":"System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip","publication_year":2017,"publication_date":"2017-09-20","ids":{"openalex":"https://openalex.org/W2754086592","doi":"https://doi.org/10.1145/3130218.3130238","mag":"2754086592"},"language":"en","primary_location":{"id":"doi:10.1145/3130218.3130238","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3130218.3130238","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=3130238&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://dl.acm.org/ft_gateway.cfm?id=3130238&type=pdf","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010816599","display_name":"Young Jin Yoon","orcid":"https://orcid.org/0000-0003-4440-4069"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Young Jin Yoon","raw_affiliation_strings":["Department of Computer Science, Columbia University, New York, New York and Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, New York and Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086890914","display_name":"Paolo Mantovani","orcid":"https://orcid.org/0000-0002-1901-8732"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paolo Mantovani","raw_affiliation_strings":["Department of Computer Science, Columbia University, New York, New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, New York","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009992367","display_name":"Luca P. Carloni","orcid":"https://orcid.org/0000-0001-5600-8931"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luca P. Carloni","raw_affiliation_strings":["Department of Computer Science, Columbia University, New York, New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, New York","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0985,"has_fulltext":true,"cited_by_count":10,"citation_normalized_percentile":{"value":0.81272048,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8015049695968628},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.8014205694198608},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7370312213897705},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7219655513763428},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6768717169761658},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6535618901252747},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6170153617858887},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.5826074481010437},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5801515579223633},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.45200297236442566},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4433083236217499}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8015049695968628},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.8014205694198608},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7370312213897705},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7219655513763428},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6768717169761658},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6535618901252747},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6170153617858887},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.5826074481010437},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5801515579223633},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.45200297236442566},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4433083236217499},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3130218.3130238","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3130218.3130238","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=3130238&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3130218.3130238","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3130218.3130238","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=3130238&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6728889783","display_name":null,"funder_award_id":"R0011-13-C-0003","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G7810979390","display_name":null,"funder_award_id":"1219001","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G8884422206","display_name":null,"funder_award_id":"2013-MA-2384","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2754086592.pdf","grobid_xml":"https://content.openalex.org/works/W2754086592.grobid-xml"},"referenced_works_count":21,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1600358781","https://openalex.org/W1941458583","https://openalex.org/W1974554881","https://openalex.org/W1976878754","https://openalex.org/W1983394510","https://openalex.org/W2062173292","https://openalex.org/W2062819906","https://openalex.org/W2099399959","https://openalex.org/W2118597853","https://openalex.org/W2124125370","https://openalex.org/W2136119421","https://openalex.org/W2140085060","https://openalex.org/W2148333560","https://openalex.org/W2149882772","https://openalex.org/W2153818151","https://openalex.org/W2157985422","https://openalex.org/W2168113051","https://openalex.org/W2170116489","https://openalex.org/W2397193845","https://openalex.org/W2413263386"],"related_works":["https://openalex.org/W1934552808","https://openalex.org/W2293483919","https://openalex.org/W4230458348","https://openalex.org/W3198758847","https://openalex.org/W1581055755","https://openalex.org/W2144357574","https://openalex.org/W2059569687","https://openalex.org/W1966325333","https://openalex.org/W2124403023","https://openalex.org/W2533063779"],"abstract_inverted_index":{"The":[0],"network-on-Chip":[1],"(NoC)":[2],"is":[3],"a":[4,14,29,45,53,89],"critical":[5],"subsystem":[6],"for":[7,17,52],"many":[8],"large-scale":[9],"systems-on-chip":[10],"(SoC).":[11],"We":[12,56,73],"present":[13],"complete":[15,83],"framework":[16],"the":[18,25,59,78],"design":[19],"and":[20,70],"optimization":[21],"of":[22,31,47,62,81],"NoCs":[23],"at":[24],"system-level.":[26],"By":[27],"combining":[28],"library":[30],"pre-designed":[32],"configurable":[33],"NoC":[34,50,71],"modules":[35],"specified":[36],"in":[37],"SystemC":[38],"with":[39,77],"high-level":[40],"synthesis,":[41],"we":[42],"can":[43],"generate":[44],"variety":[46],"alternative":[48],"2D-Mesh":[49],"architectures":[51],"given":[54],"SoC.":[55],"also":[57],"support":[58],"automatic":[60],"synthesis":[61],"network":[63],"interfaces":[64],"to":[65],"translate":[66],"between":[67],"IP-specific":[68],"messages":[69],"flits.":[72],"demonstrate":[74],"our":[75],"approach":[76],"design-space":[79],"exploration":[80],"two":[82],"SoCs":[84],"running":[85],"complex":[86],"applications":[87],"on":[88],"high-end":[90],"FPGA":[91],"board.":[92]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
