{"id":"https://openalex.org/W2765130487","doi":"https://doi.org/10.1145/3125501.3125514","title":"Code-size-aware mapping for synchronous dataflow graphs on multicore systems","display_name":"Code-size-aware mapping for synchronous dataflow graphs on multicore systems","publication_year":2017,"publication_date":"2017-10-15","ids":{"openalex":"https://openalex.org/W2765130487","doi":"https://doi.org/10.1145/3125501.3125514","mag":"2765130487"},"language":"en","primary_location":{"id":"doi:10.1145/3125501.3125514","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3125501.3125514","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037648163","display_name":"Mingze Ma","orcid":"https://orcid.org/0000-0003-1241-3147"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Mingze Ma","raw_affiliation_strings":["The University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"The University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079821707","display_name":"Rizos Sakellariou","orcid":"https://orcid.org/0000-0002-6104-6649"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Rizos Sakellariou","raw_affiliation_strings":["The University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"The University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5037648163"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.2253,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.51625193,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8899908661842346},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.842636227607727},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6193730235099792},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6037110090255737},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5679206848144531},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5481772422790527},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5255897045135498},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48525047302246094},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4777909219264984},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4492821991443634},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.42907634377479553},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10208374261856079},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07725420594215393}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8899908661842346},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.842636227607727},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6193730235099792},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6037110090255737},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5679206848144531},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5481772422790527},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5255897045135498},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48525047302246094},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4777909219264984},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4492821991443634},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.42907634377479553},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10208374261856079},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07725420594215393},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3125501.3125514","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3125501.3125514","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/0351101e-df6f-47fb-9b70-481650d8af4f","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/0351101e-df6f-47fb-9b70-481650d8af4f","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Ma, M & Sakellariou, R 2017, Work-in-progress : Code-size-aware mapping for Synchronous dataflow graphs on multicore systems. in Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017., 3125514, Association for Computing Machinery, 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Korea, Republic of, 15/10/17. https://doi.org/10.1145/3125501.3125514","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:pure.atira.dk:publications/0351101e-df6f-47fb-9b70-481650d8af4f","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=85035358209&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Ma, M & Sakellariou, R 2017, Work-in-progress : Code-size-aware mapping for Synchronous dataflow graphs on multicore systems. in Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017., 3125514, Association for Computing Machinery, 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Korea, Republic of, 15/10/17. https://doi.org/10.1145/3125501.3125514","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2015912445","https://openalex.org/W2115141746","https://openalex.org/W2164084134","https://openalex.org/W2257028583","https://openalex.org/W2558719560"],"related_works":["https://openalex.org/W2293118914","https://openalex.org/W2998381397","https://openalex.org/W4236419692","https://openalex.org/W3167919718","https://openalex.org/W4251718783","https://openalex.org/W2171015181","https://openalex.org/W4239447582","https://openalex.org/W1484403103","https://openalex.org/W2521947294","https://openalex.org/W2907307640"],"abstract_inverted_index":{"Synchronous":[0],"Dataflow":[1],"Graphs":[2],"(SDFGs)":[3],"are":[4,17],"widely":[5],"used":[6,88],"to":[7,56,73,94],"model":[8],"streaming":[9],"applications":[10],"(e.g.":[11],"digital":[12],"signal":[13],"processing":[14],"applications),":[15],"which":[16],"commonly":[18],"executed":[19],"by":[20],"embedded":[21,33],"systems.":[22,34,82],"The":[23,83],"usage":[24],"of":[25,38,45,61,99],"on-chip":[26,46,62],"resources":[27],"is":[28,41,52,71,86],"always":[29],"strictly":[30],"constrained":[31],"in":[32],"As":[35],"the":[36,58,75,96,100,106,116],"cost":[37],"instruction":[39],"memory":[40],"a":[42,67,90],"significant":[43,110],"part":[44],"resource":[47],"costs,":[48],"code":[49,76,97,111],"size":[50,77,98,112],"reduction":[51,113],"an":[53],"effective":[54],"way":[55],"control":[57],"overall":[59],"costs":[60],"resources.":[63],"In":[64,103],"this":[65],"work,":[66],"code-size-aware":[68],"mapping":[69,84],"heuristic":[70,85,93,108],"proposed":[72,107],"decrease":[74,95],"for":[78,114],"SDFGs":[79,118],"on":[80],"multicore":[81],"jointly":[87],"with":[89],"self-timed":[91],"scheduling":[92],"original":[101],"schedule.":[102],"preliminary":[104],"experiments,":[105],"achieves":[109],"all":[115],"tested":[117],"without":[119],"affecting":[120],"throughput.":[121]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2017-11-10T00:00:00"}