{"id":"https://openalex.org/W2780978152","doi":"https://doi.org/10.1145/3120895.3120918","title":"High-level Synthesis based on Parallel Design Patterns using a Functional Language","display_name":"High-level Synthesis based on Parallel Design Patterns using a Functional Language","publication_year":2017,"publication_date":"2017-06-07","ids":{"openalex":"https://openalex.org/W2780978152","doi":"https://doi.org/10.1145/3120895.3120918","mag":"2780978152"},"language":"en","primary_location":{"id":"doi:10.1145/3120895.3120918","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3120895.3120918","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109427367","display_name":"Morihiro Kuga","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Morihiro Kuga","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088463220","display_name":"Kansuke Fukuda","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kansuke Fukuda","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki Amagasaki","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031401749","display_name":"Toshinori Sueyoshi","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori Sueyoshi","raw_affiliation_strings":["Kumamoto University, Kumamoto, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2312,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.5521649,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/programmer","display_name":"Programmer","score":0.8596161007881165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8060951232910156},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7541075944900513},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.7305565476417542},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6940180063247681},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6200733184814453},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5761421322822571},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5198448300361633},{"id":"https://openalex.org/keywords/high-level-programming-language","display_name":"High-level programming language","score":0.5046144723892212},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4643670916557312},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.44351664185523987},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.42307808995246887},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42145881056785583},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41570404171943665},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.396902471780777},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3463899493217468},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.3351789116859436},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24915313720703125},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.084646075963974}],"concepts":[{"id":"https://openalex.org/C2778514511","wikidata":"https://www.wikidata.org/wiki/Q1374194","display_name":"Programmer","level":2,"score":0.8596161007881165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8060951232910156},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7541075944900513},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.7305565476417542},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6940180063247681},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6200733184814453},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5761421322822571},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5198448300361633},{"id":"https://openalex.org/C19024347","wikidata":"https://www.wikidata.org/wiki/Q211496","display_name":"High-level programming language","level":3,"score":0.5046144723892212},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4643670916557312},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.44351664185523987},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.42307808995246887},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42145881056785583},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41570404171943665},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.396902471780777},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3463899493217468},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.3351789116859436},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24915313720703125},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.084646075963974}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3120895.3120918","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3120895.3120918","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1583099307","https://openalex.org/W1970032753","https://openalex.org/W2000921084","https://openalex.org/W2036940992","https://openalex.org/W2049600101","https://openalex.org/W2102075452","https://openalex.org/W2127699991","https://openalex.org/W2129988636","https://openalex.org/W2133156997","https://openalex.org/W2133697335","https://openalex.org/W2141597697","https://openalex.org/W2166029537","https://openalex.org/W2184799168","https://openalex.org/W2263852834","https://openalex.org/W2515406844","https://openalex.org/W4245440340","https://openalex.org/W4251523731","https://openalex.org/W4256629673"],"related_works":["https://openalex.org/W2000188956","https://openalex.org/W2491368619","https://openalex.org/W3127258852","https://openalex.org/W3109783146","https://openalex.org/W2181818047","https://openalex.org/W2132512458","https://openalex.org/W2133642747","https://openalex.org/W1547989843","https://openalex.org/W2066253757","https://openalex.org/W2105118350"],"abstract_inverted_index":{"Logic-circuit":[0],"integration":[1],"of":[2,35],"a":[3,58],"field-programmable":[4],"gate":[5],"array":[6],"(FPGA)":[7],"has":[8],"grown":[9],"considerably":[10],"with":[11],"improvements":[12],"in":[13],"semiconductor":[14],"technology.":[15],"High-level":[16],"synthesis":[17],"(HLS)":[18],"is":[19],"now":[20],"widely":[21],"used":[22],"to":[23,28,73,84,98],"implement":[24],"complex":[25],"FPGA":[26],"applications":[27],"increase":[29],"design":[30,74],"efficiency,":[31],"taking":[32],"the":[33,82,91,96],"place":[34],"typical":[36],"register-transfer":[37],"level":[38],"(RTL)":[39],"design.":[40],"Most":[41],"HLS":[42],"tools":[43,67,79],"support":[44],"C-like":[45,59],"languages":[46,72],"such":[47,78],"as":[48],"C/C++,":[49],"SystemC,":[50],"OpenCL,":[51],"and":[52,87],"CUDA.":[53],"However,":[54,76],"coarse-grain":[55],"parallelism":[56],"from":[57],"language":[60],"cannot":[61],"be":[62],"extracted":[63],"easily,":[64],"hence":[65],"some":[66],"use":[68],"explicitly":[69],"parallel":[70],"programming":[71],"hardware.":[75],"all":[77],"rely":[80],"on":[81,90],"programmer":[83,97],"correctly":[85],"parallelize":[86],"perform":[88],"optimizations":[89],"application,":[92],"which":[93],"often":[94],"forces":[95],"acquire":[99],"hardware-design":[100],"knowledge.":[101]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-12T08:23:45.883708","created_date":"2025-10-10T00:00:00"}