{"id":"https://openalex.org/W2777917129","doi":"https://doi.org/10.1145/3120895.3120908","title":"HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis","display_name":"HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis","publication_year":2017,"publication_date":"2017-06-07","ids":{"openalex":"https://openalex.org/W2777917129","doi":"https://doi.org/10.1145/3120895.3120908","mag":"2777917129"},"language":"en","primary_location":{"id":"doi:10.1145/3120895.3120908","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3120895.3120908","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072516473","display_name":"Sajjad Nouri","orcid":"https://orcid.org/0000-0002-5925-3681"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Sajjad Nouri","raw_affiliation_strings":["Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053320135","display_name":"Jens Rettkowski","orcid":"https://orcid.org/0009-0002-4926-1984"},"institutions":[{"id":"https://openalex.org/I904495901","display_name":"Ruhr University Bochum","ror":"https://ror.org/04tsk2644","country_code":"DE","type":"education","lineage":["https://openalex.org/I904495901"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jens Rettkowski","raw_affiliation_strings":["Application-Specific Multi-Core Architectures (MCA) Group, Ruhr-Universit\u00e4t Bochum, Bochum, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Application-Specific Multi-Core Architectures (MCA) Group, Ruhr-Universit\u00e4t Bochum, Bochum, Germany","institution_ids":["https://openalex.org/I904495901"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060626530","display_name":"Diana G\u00f6hringer","orcid":"https://orcid.org/0000-0003-2571-8441"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Diana G\u00f6hringer","raw_affiliation_strings":["Chair for Adaptive Dynamic Systems, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair for Adaptive Dynamic Systems, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6936,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71695071,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8079580068588257},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6617845296859741},{"id":"https://openalex.org/keywords/orthogonal-frequency-division-multiplexing","display_name":"Orthogonal frequency-division multiplexing","score":0.6373680830001831},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.56224524974823},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5433829426765442},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4841378629207611},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4652593731880188},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.4313996136188507},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.42277970910072327},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.15997347235679626},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11975359916687012}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8079580068588257},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6617845296859741},{"id":"https://openalex.org/C40409654","wikidata":"https://www.wikidata.org/wiki/Q375889","display_name":"Orthogonal frequency-division multiplexing","level":3,"score":0.6373680830001831},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.56224524974823},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5433829426765442},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4841378629207611},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4652593731880188},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.4313996136188507},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.42277970910072327},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.15997347235679626},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11975359916687012},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3120895.3120908","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3120895.3120908","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1579958198","https://openalex.org/W1595104169","https://openalex.org/W1974927420","https://openalex.org/W2003313945","https://openalex.org/W2029320999","https://openalex.org/W2061171222","https://openalex.org/W2066762506","https://openalex.org/W2089203444","https://openalex.org/W2108571327","https://openalex.org/W2121844610","https://openalex.org/W2122620713","https://openalex.org/W2133920396","https://openalex.org/W2166613240","https://openalex.org/W2580686730","https://openalex.org/W2614808262","https://openalex.org/W3099072440","https://openalex.org/W3184755664"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248","https://openalex.org/W2367794224","https://openalex.org/W2389916899","https://openalex.org/W2072850836","https://openalex.org/W1968650434","https://openalex.org/W2105610663","https://openalex.org/W1996607072"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,6,28,50,134],"implementation":[4,102],"of":[5,85,103,128],"Orthogonal":[7],"Frequency-Division":[8],"Multiplexing":[9],"(OFDM)":[10],"receiver":[11,64,82,105,132],"using":[12],"the":[13,42,62,74,77,101,115,122,125,129,140],"high-level":[14],"synthesis":[15],"tool,":[16],"from":[17],"Xilinx":[18],"called":[19],"Software":[20],"Defined":[21],"System-on-Chip":[22],"(SDSoC).":[23],"The":[24,80],"Zynq":[25],"SoCs":[26],"containing":[27],"ARM":[29,78],"processor":[30],"besides":[31],"a":[32,91],"Field":[33],"Programmable":[34],"Gate":[35],"Array":[36],"(FPGA)":[37],"are":[38,107],"introduced":[39],"to":[40,70,94,139],"improve":[41],"system":[43,96],"performance":[44],"and":[45,76,112],"power":[46],"efficiency.":[47],"SDSoC":[48],"provides":[49],"embedded":[51,59],"C/C++":[52,68],"application":[53],"programming":[54],"interface":[55],"for":[56],"developing":[57],"heterogeneous":[58],"systems.":[60],"Thus,":[61],"OFDM":[63,81,104],"is":[65,83],"written":[66],"in":[67],"code":[69],"be":[71],"realizable":[72],"on":[73,109,121],"FPGA":[75],"processor.":[79],"composed":[84],"computationally":[86],"intensive":[87],"tasks":[88],"which":[89],"requires":[90],"HW/SW":[92],"co-design":[93],"fulfill":[95],"requirements.":[97],"In":[98],"this":[99],"work,":[100],"blocks":[106],"evaluated":[108],"ZC706":[110],"board":[111],"compared":[113,138],"against":[114],"Heterogeneous":[116],"Accelerator-Rich":[117],"Platform":[118],"(HARP).":[119],"Based":[120],"achieved":[123],"results,":[124],"complete":[126],"execution":[127],"IEEE":[130],"802.11a/g":[131],"shows":[133],"overall":[135],"speed-up":[136],"3.49X":[137],"HARP":[141],"platform.":[142]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}