{"id":"https://openalex.org/W2780479386","doi":"https://doi.org/10.1145/3120895.3120902","title":"High Speed Performance Estimation of Embedded Hard-core Processors in FPGA-based SoCs","display_name":"High Speed Performance Estimation of Embedded Hard-core Processors in FPGA-based SoCs","publication_year":2017,"publication_date":"2017-06-07","ids":{"openalex":"https://openalex.org/W2780479386","doi":"https://doi.org/10.1145/3120895.3120902","mag":"2780479386"},"language":"en","primary_location":{"id":"doi:10.1145/3120895.3120902","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3120895.3120902","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054161727","display_name":"Deshya Wijesundera","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Deshya Wijesundera","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053956849","display_name":"Achintha Ihalage","orcid":"https://orcid.org/0000-0002-4250-187X"},"institutions":[{"id":"https://openalex.org/I195740183","display_name":"University of Moratuwa","ror":"https://ror.org/0491f5305","country_code":"LK","type":"education","lineage":["https://openalex.org/I195740183"]}],"countries":["LK"],"is_corresponding":false,"raw_author_name":"Achintha Ihalage","raw_affiliation_strings":["University of Moratuwa, Sri Lanka"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Moratuwa, Sri Lanka","institution_ids":["https://openalex.org/I195740183"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101468284","display_name":"Alok Prakash","orcid":"https://orcid.org/0000-0001-8257-2974"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Alok Prakash","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070475093","display_name":"Thambipillai Srikanthan","orcid":"https://orcid.org/0000-0003-3664-4345"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Thambipillai Srikanthan","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20255643,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8270620703697205},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7517545819282532},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7072856426239014},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6644631028175354},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.6007486581802368},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.55643230676651},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5495603680610657},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.47903695702552795},{"id":"https://openalex.org/keywords/vendor","display_name":"Vendor","score":0.46626123785972595},{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.4529584050178528},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3334636092185974},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.28719407320022583}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8270620703697205},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7517545819282532},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7072856426239014},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6644631028175354},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.6007486581802368},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.55643230676651},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5495603680610657},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.47903695702552795},{"id":"https://openalex.org/C2777338717","wikidata":"https://www.wikidata.org/wiki/Q1762621","display_name":"Vendor","level":2,"score":0.46626123785972595},{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.4529584050178528},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3334636092185974},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.28719407320022583},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3120895.3120902","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3120895.3120902","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4699999988079071,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W808428043","https://openalex.org/W1981251955","https://openalex.org/W1986491730","https://openalex.org/W2087183850","https://openalex.org/W2097197938","https://openalex.org/W2143324082","https://openalex.org/W2147099788","https://openalex.org/W2150427624","https://openalex.org/W2156499539","https://openalex.org/W2165194057","https://openalex.org/W2393824727","https://openalex.org/W2486372501","https://openalex.org/W2527484378","https://openalex.org/W2612563559","https://openalex.org/W2615016564","https://openalex.org/W4232048937"],"related_works":["https://openalex.org/W2371772824","https://openalex.org/W2350519679","https://openalex.org/W2169881414","https://openalex.org/W2042843335","https://openalex.org/W2108598117","https://openalex.org/W634388121","https://openalex.org/W2181598986","https://openalex.org/W2976906885","https://openalex.org/W2912613323","https://openalex.org/W2143461502"],"abstract_inverted_index":{"The":[0],"embedded":[1,63],"hard-core":[2,37],"processors":[3,64],"beside":[4],"the":[5,21,25,29,122,135],"traditional":[6],"FPGA":[7,30,131],"fabric":[8,31],"in":[9,126,150],"FPGA-based":[10],"System-on-Chip":[11],"(SoC)":[12],"devices":[13],"make":[14,93],"them":[15],"an":[16,75,78,142],"attractive":[17],"alternative":[18],"for":[19,32,55,101,116],"realizing":[20],"software":[22],"portions":[23],"of":[24,61,71,145],"application":[26,76],"while":[27],"using":[28],"hardware":[33],"acceleration.":[34],"However,":[35],"several":[36],"processor":[38,73,125],"options":[39],"are":[40],"becoming":[41],"available":[42],"from":[43,48,134],"different":[44],"manufacturers":[45],"or":[46],"even":[47],"a":[49,72,102,110,127,153],"single":[50],"vendor.":[51],"This":[52],"necessitates":[53],"methodologies":[54],"rapid":[56,69],"and":[57,89],"reliable":[58],"performance":[59,100,113],"estimation":[60,114],"such":[62,84,117],"so":[65],"as":[66,85],"to":[67,96],"enable":[68],"selection":[70],"given":[74,103],"at":[77],"early":[79],"design":[80],"stage.":[81],"Architectural":[82],"features":[83],"superscalar,":[86],"multi":[87],"issue":[88],"out-of-order":[90],"processing,":[91],"however,":[92],"it":[94],"challenging":[95],"accurately":[97],"estimate":[98],"their":[99],"application.":[104],"In":[105],"this":[106],"paper,":[107],"we":[108],"propose":[109],"high":[111],"speed":[112],"framework":[115],"processors.":[118],"Experimental":[119],"results":[120],"on":[121],"ARM":[123],"Cortex-A9":[124],"Xilinx":[128],"Zynq":[129],"SoC":[130],"executing":[132],"applications":[133],"widely":[136],"used":[137],"CHStone":[138],"benchmark":[139],"suite":[140],"show":[141],"average":[143],"error":[144],"less":[146],"than":[147],"6%,":[148],"completed":[149],"just":[151],"over":[152],"minute.":[154]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
