{"id":"https://openalex.org/W2767200595","doi":"https://doi.org/10.1145/3109984.3110022","title":"Sleep convention logic isochronic fork","display_name":"Sleep convention logic isochronic fork","publication_year":2017,"publication_date":"2017-08-28","ids":{"openalex":"https://openalex.org/W2767200595","doi":"https://doi.org/10.1145/3109984.3110022","mag":"2767200595"},"language":"en","primary_location":{"id":"doi:10.1145/3109984.3110022","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3109984.3110022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070461364","display_name":"Ricardo Aquino Guazzelli","orcid":null},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Ricardo A. Guazzelli","raw_affiliation_strings":["Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101963901","display_name":"Matheus T. Moreira","orcid":"https://orcid.org/0000-0001-5030-9215"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Matheus T. Moreira","raw_affiliation_strings":["Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028824039","display_name":"Walter Lau Neto","orcid":"https://orcid.org/0000-0002-9349-4964"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Walter Lau Neto","raw_affiliation_strings":["Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072149252","display_name":"Ney Calazans","orcid":"https://orcid.org/0000-0002-0467-4294"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Ney L. V. Calazans","raw_affiliation_strings":["Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul - Porto Alegre - RS - Brazil","institution_ids":["https://openalex.org/I45643870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5070461364"],"corresponding_institution_ids":["https://openalex.org/I45643870"],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.52367724,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"103","last_page":"109"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6949158310890198},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6857359409332275},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5729649662971497},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5657460689544678},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5523062348365784},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4833238124847412},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4643547832965851},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37901896238327026},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3689928352832794},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2164534330368042},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17642813920974731},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1701239049434662},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1640152633190155}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6949158310890198},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6857359409332275},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5729649662971497},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5657460689544678},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5523062348365784},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4833238124847412},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4643547832965851},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37901896238327026},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3689928352832794},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2164534330368042},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17642813920974731},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1701239049434662},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1640152633190155},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3109984.3110022","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3109984.3110022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G8864719584","display_name":null,"funder_award_id":"312556/2014 4","funder_id":"https://openalex.org/F4320322025","funder_display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico"}],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W232434517","https://openalex.org/W1466029356","https://openalex.org/W1512610407","https://openalex.org/W1604826642","https://openalex.org/W1882862660","https://openalex.org/W1999082644","https://openalex.org/W2001030538","https://openalex.org/W2004113442","https://openalex.org/W2083950284","https://openalex.org/W2085176118","https://openalex.org/W2117299791","https://openalex.org/W2134829921","https://openalex.org/W2171199949","https://openalex.org/W2171825402","https://openalex.org/W2487142227","https://openalex.org/W2679572621"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W1993985975","https://openalex.org/W2146990170","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2085028021","https://openalex.org/W2138474603","https://openalex.org/W3094139610","https://openalex.org/W937897205","https://openalex.org/W2380707529"],"abstract_inverted_index":{"Asynchronous":[0],"quasi-delay-insensitive":[1],"(QDI)":[2],"circuits":[3,35,121],"are":[4,36,46],"a":[5,108],"promising":[6,38],"solution":[7],"for":[8,39],"coping":[9],"with":[10],"aggressive":[11],"process":[12],"variations":[13],"faced":[14],"by":[15],"modern":[16],"technologies,":[17],"as":[18],"they":[19],"can":[20,68],"gracefully":[21],"accommodate":[22],"gate":[23],"and":[24,63,79,126],"wire":[25],"delay":[26],"variations.":[27],"Furthermore,":[28],"due":[29],"to":[30,147],"their":[31],"inherent":[32],"robustness,":[33],"such":[34,143],"also":[37,138],"deep":[40],"voltage":[41,157],"scaling":[42],"applications,":[43],"where":[44],"delays":[45],"orders":[47],"of":[48,72,75,103,120,151],"magnitude":[49],"larger.":[50],"However,":[51],"QDI":[52,112],"design":[53,76,87,113],"has":[54],"an":[55,101],"Achilles":[56],"heel,":[57],"which":[58],"is":[59,100,145],"its":[60],"associated":[61,128],"area":[62],"power":[64],"overhead":[65],"penalties.":[66],"These":[67],"hamper":[69],"the":[70,89,104,118],"adoption":[71],"this":[73],"kind":[74],"in":[77],"current":[78],"future":[80],"technologies.":[81],"A":[82],"recently":[83],"proposed":[84],"asynchronous":[85,110],"circuit":[86,111],"template,":[88],"Sleep":[90],"Convention":[91,106],"Logic":[92],"(SCL),":[93],"does":[94],"reduce":[95],"these":[96,152],"overheads":[97],"significantly.":[98],"SCL":[99],"enhancement":[102],"Null":[105],"Logic,":[107],"well-known":[109],"template.":[114],"This":[115],"paper":[116,137],"analyzes":[117],"architecture":[119],"based":[122],"on":[123],"SCL,":[124],"identifies":[125],"models":[127],"timing":[129],"constraints":[130,144],"that":[131,141],"were":[132],"not":[133],"described":[134],"before.":[135],"The":[136],"shows":[139],"experimentally":[140],"respecting":[142],"fundamental":[146],"guarantee":[148],"correct":[149],"operation":[150],"circuits,":[153],"especially":[154],"under":[155],"low":[156],"supplies.":[158]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}