{"id":"https://openalex.org/W2766193625","doi":"https://doi.org/10.1145/3109984.3109997","title":"Hardware and software infrastructure to implement many-core systems in modern FPGAs","display_name":"Hardware and software infrastructure to implement many-core systems in modern FPGAs","publication_year":2017,"publication_date":"2017-08-28","ids":{"openalex":"https://openalex.org/W2766193625","doi":"https://doi.org/10.1145/3109984.3109997","mag":"2766193625"},"language":"en","primary_location":{"id":"doi:10.1145/3109984.3109997","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3109984.3109997","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004981243","display_name":"Felipe T. Bortolon","orcid":"https://orcid.org/0000-0001-6288-978X"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Felipe T. Bortolon","raw_affiliation_strings":["PUCRS - Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"PUCRS - Porto Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025418231","display_name":"Fernando Moraes","orcid":"https://orcid.org/0000-0001-6126-6847"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fernando G. Moraes","raw_affiliation_strings":["PUCRS - Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"PUCRS - Porto Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5004981243"],"corresponding_institution_ids":["https://openalex.org/I45643870"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16013811,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"83"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.883213996887207},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.768231987953186},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7543842196464539},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.709551215171814},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.6284801959991455},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6224496960639954},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.5679164528846741},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5446010828018188},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5408864617347717},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5143615007400513},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25989919900894165},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.13510116934776306}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.883213996887207},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.768231987953186},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7543842196464539},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.709551215171814},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.6284801959991455},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6224496960639954},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.5679164528846741},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5446010828018188},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5408864617347717},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5143615007400513},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25989919900894165},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.13510116934776306},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3109984.3109997","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3109984.3109997","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G3549603996","display_name":null,"funder_award_id":"302531/2016-5","funder_id":"https://openalex.org/F4320322025","funder_display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico"}],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1997023110","https://openalex.org/W2039481119","https://openalex.org/W2113302371","https://openalex.org/W2149777400","https://openalex.org/W4299387946"],"related_works":["https://openalex.org/W2159103767","https://openalex.org/W3103981520","https://openalex.org/W200972441","https://openalex.org/W2038220260","https://openalex.org/W1857140530","https://openalex.org/W1545578515","https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W1544665014"],"abstract_inverted_index":{"Many-core":[0],"systems":[1,7,20,91,110],"are":[2,72],"increasingly":[3],"popular":[4],"in":[5,111],"embedded":[6,50,69,115],"due":[8],"to":[9,14,30,44,74,85,103,107,120,126,141],"their":[10],"high-performance":[11],"and":[12,125],"flexibility":[13,29],"execute":[15,75],"different":[16],"workloads.":[17],"These":[18],"many-core":[19,90,109,123],"provide":[21,59],"a":[22,60,129],"rich":[23,61],"processing":[24],"fabric":[25],"but":[26],"lack":[27],"the":[28,83,87,93,122,139,147],"accelerate":[31],"critical":[32],"operations":[33],"with":[34,53,92,128],"dedicated":[35,143],"hardware":[36,63,144],"cores.":[37,56],"Modern":[38],"Field":[39],"Programmable":[40],"Gate-Arrays":[41],"(FPGAs)":[42],"evolved":[43],"more":[45],"than":[46],"reconfigurable":[47,62],"devices,":[48],"providing":[49],"hard-core":[51,70,116],"processors":[52,71],"several":[54],"IP":[55],"While":[57],"FPGAs":[58,81],"fabric,":[64],"only":[65],"one":[66],"or":[67],"two":[68],"available":[73],"complex":[76],"software":[77],"applications.":[78],"Therefore,":[79],"modern":[80,112],"offer":[82],"possibility":[84],"merge":[86],"benefits":[88],"of":[89,95,99],"reconfigurability":[94],"FPGAs.":[96,113],"The":[97],"goal":[98],"this":[100],"paper":[101],"is":[102,118,136],"present":[104],"an":[105],"infrastructure":[106],"implement":[108],"An":[114],"processor":[117],"used":[119],"manage":[121],"area,":[124],"communicate":[127],"host":[130],"computer.":[131],"A":[132],"functional":[133],"proof-of-concept":[134],"system":[135],"presented,":[137],"paving":[138],"way":[140],"connect":[142],"IPs":[145],"into":[146],"NoC.":[148]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}