{"id":"https://openalex.org/W2782868422","doi":"https://doi.org/10.1145/3093741","title":"High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors","display_name":"High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors","publication_year":2018,"publication_date":"2018-01-09","ids":{"openalex":"https://openalex.org/W2782868422","doi":"https://doi.org/10.1145/3093741","mag":"2782868422"},"language":"en","primary_location":{"id":"doi:10.1145/3093741","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3093741","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000808423","display_name":"Henry Wong","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Henry Wong","raw_affiliation_strings":["University of Toronto, Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["University of Toronto, Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090184149","display_name":"Jonathan Rose","orcid":"https://orcid.org/0000-0002-3551-2175"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jonathan Rose","raw_affiliation_strings":["University of Toronto, Toronto, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5000808423"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.5049,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.58139819,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"11","issue":"1","first_page":"1","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8836237192153931},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6710020899772644},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6117004752159119},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6096562147140503},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5006673336029053},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.484052836894989},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.4465816915035248},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.4457792639732361},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.4366358816623688},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4337434768676758},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41413554549217224},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41291341185569763},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13178065419197083}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8836237192153931},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6710020899772644},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6117004752159119},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6096562147140503},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5006673336029053},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.484052836894989},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.4465816915035248},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.4457792639732361},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.4366358816623688},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4337434768676758},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41413554549217224},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41291341185569763},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13178065419197083},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3093741","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3093741","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1562605315","https://openalex.org/W1582324226","https://openalex.org/W1686420892","https://openalex.org/W1976264025","https://openalex.org/W1991010395","https://openalex.org/W1991826962","https://openalex.org/W2002747242","https://openalex.org/W2030959856","https://openalex.org/W2039545941","https://openalex.org/W2039631685","https://openalex.org/W2053425359","https://openalex.org/W2112841617","https://openalex.org/W2121539621","https://openalex.org/W2123413169","https://openalex.org/W2131556574","https://openalex.org/W2140782438","https://openalex.org/W2153098282","https://openalex.org/W2156263417","https://openalex.org/W2161864047","https://openalex.org/W2164376452","https://openalex.org/W2516980303","https://openalex.org/W2989484426","https://openalex.org/W4232751114","https://openalex.org/W4240643561","https://openalex.org/W4243872270","https://openalex.org/W4285719527","https://openalex.org/W6770474004"],"related_works":["https://openalex.org/W37057355","https://openalex.org/W2294153958","https://openalex.org/W2108104128","https://openalex.org/W2121109048","https://openalex.org/W2087838646","https://openalex.org/W3144235744","https://openalex.org/W3138214237","https://openalex.org/W2088743628","https://openalex.org/W3015018880","https://openalex.org/W2286517267"],"abstract_inverted_index":{"Soft":[0],"processors":[1,87],"have":[2],"a":[3,140,144,197],"role":[4,42],"to":[5,27,109,121,161,186,201],"play":[6],"in":[7,60,85,92],"simplifying":[8],"field-programmable":[9],"gate":[10],"array":[11],"(FPGA)":[12],"application":[13],"design":[14,101,182],"as":[15,172],"they":[16],"can":[17,164],"be":[18,165],"deployed":[19],"only":[20],"when":[21,44],"needed,":[22],"and":[23,29,118,128,131,192],"it":[24],"is":[25,107],"easier":[26],"write":[28],"debug":[30],"single-threaded":[31],"software":[32],"code":[33],"than":[34],"create":[35],"hardware.":[36],"The":[37],"breadth":[38],"of":[39,47,196],"this":[40,75],"second":[41],"increases":[43],"the":[45,48,53,61,99,104,137,168,173,184,190],"performance":[46,195],"soft":[49,86,177,198,204],"processor":[50,113,178],"increases,":[51],"yet":[52],"sophisticated":[54],"out-of-order":[55,83],"superscalar":[56],"approaches":[57],"that":[58,155],"arrived":[59],"mid-1990s":[62],"are":[63],"not":[64],"employed,":[65],"despite":[66],"their":[67],"area":[68],"cost":[69],"now":[70],"being":[71],"easily":[72],"tolerable.":[73],"In":[74],"article,":[76],"we":[77,153],"take":[78],"an":[79,93],"important":[80],"step":[81],"toward":[82],"execution":[84],"by":[88],"exploring":[89],"instruction":[90],"scheduling":[91,114],"FPGA":[94],"substrate.":[95],"This":[96,180],"differs":[97],"from":[98],"hard-processor":[100],"problem":[102],"because":[103],"logic":[105],"substrate":[106],"restricted":[108],"LUTs,":[110],"whereas":[111],"hard":[112],"circuits":[115],"employ":[116],"CAM":[117],"wired-OR":[119],"structures":[120,135],"great":[122],"benefit.":[123],"We":[124],"discuss":[125],"both":[126,189],"circuit":[127,134],"microarchitectural":[129],"trade-offs":[130],"compare":[132],"three":[133],"for":[136],"scheduler,":[138],"including":[139],"new":[141],"structure":[142],"called":[143],"fused-logic":[145],"matrix":[146],"scheduler":[147],".":[148],"Using":[149],"our":[150],"optimized":[151],"circuits,":[152],"show":[154],"four-issue":[156],"distributed":[157],"schedulers":[158],"with":[159,167],"up":[160],"54":[162],"entries":[163],"built":[166],"same":[169],"cycle":[170],"time":[171],"commercial":[174,203],"Nios":[175],"II/f":[176],"(240MHz).":[179],"careful":[181],"has":[183],"potential":[185],"significantly":[187],"increase":[188],"IPC":[191],"raw":[193],"compute":[194],"processor,":[199],"compared":[200],"current":[202],"processors.":[205]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
