{"id":"https://openalex.org/W2668120530","doi":"https://doi.org/10.1145/3092627.3092629","title":"Shakti-T","display_name":"Shakti-T","publication_year":2017,"publication_date":"2017-06-25","ids":{"openalex":"https://openalex.org/W2668120530","doi":"https://doi.org/10.1145/3092627.3092629","mag":"2668120530"},"language":"en","primary_location":{"id":"doi:10.1145/3092627.3092629","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3092627.3092629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Hardware and Architectural Support for Security and Privacy","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103757264","display_name":"Arjun Menon","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Arjun Menon","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Madras, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078079678","display_name":"Subadra Murugan","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Subadra Murugan","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Madras, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038432102","display_name":"Chester Rebeiro","orcid":"https://orcid.org/0000-0001-8063-0026"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Chester Rebeiro","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Madras, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007490713","display_name":"Neel Gala","orcid":"https://orcid.org/0000-0001-8611-6511"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Neel Gala","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Madras, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Madras, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":null,"display_name":"Kamakoti Veezhinathan","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kamakoti Veezhinathan","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Madras, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Madras, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5103757264"],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":4.5733,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.95643264,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11241","display_name":"Advanced Malware Detection Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8369646072387695},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6525253653526306},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6394239068031311},{"id":"https://openalex.org/keywords/metadata","display_name":"Metadata","score":0.5694893598556519},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5383386015892029},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.48263344168663025},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.47335290908813477},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.456584632396698},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4560328722000122},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41712820529937744},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36905813217163086},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.243728905916214},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.1977049708366394}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8369646072387695},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6525253653526306},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6394239068031311},{"id":"https://openalex.org/C93518851","wikidata":"https://www.wikidata.org/wiki/Q180160","display_name":"Metadata","level":2,"score":0.5694893598556519},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5383386015892029},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.48263344168663025},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.47335290908813477},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.456584632396698},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4560328722000122},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41712820529937744},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36905813217163086},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.243728905916214},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.1977049708366394},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3092627.3092629","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3092627.3092629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Hardware and Architectural Support for Security and Privacy","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1112477","https://openalex.org/W130708379","https://openalex.org/W220440441","https://openalex.org/W1655226010","https://openalex.org/W1825457006","https://openalex.org/W1969338270","https://openalex.org/W1973326708","https://openalex.org/W1982829328","https://openalex.org/W1987898580","https://openalex.org/W2031006315","https://openalex.org/W2084438901","https://openalex.org/W2089448621","https://openalex.org/W2090181646","https://openalex.org/W2094619820","https://openalex.org/W2096248434","https://openalex.org/W2098010707","https://openalex.org/W2098806455","https://openalex.org/W2109219878","https://openalex.org/W2112736324","https://openalex.org/W2122757982","https://openalex.org/W2128637495","https://openalex.org/W2129482816","https://openalex.org/W2141365240","https://openalex.org/W2158763360","https://openalex.org/W2160725972","https://openalex.org/W2162800072","https://openalex.org/W2165266180","https://openalex.org/W2171482413","https://openalex.org/W2171938395","https://openalex.org/W2294097286","https://openalex.org/W2586250227","https://openalex.org/W2808492852","https://openalex.org/W2978757628","https://openalex.org/W4212894444","https://openalex.org/W4230177578","https://openalex.org/W4237187719","https://openalex.org/W4239342816","https://openalex.org/W4242383889","https://openalex.org/W4245736681","https://openalex.org/W4249353546","https://openalex.org/W4299301436"],"related_works":["https://openalex.org/W2058118494","https://openalex.org/W2392768766","https://openalex.org/W2382021449","https://openalex.org/W2095118173","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2035206467","https://openalex.org/W2512308948","https://openalex.org/W2068921804"],"abstract_inverted_index":{"With":[0],"increased":[1],"usage":[2],"of":[3,75,118,135],"compute":[4],"cores":[5],"for":[6,20,34],"sensitive":[7,69],"applications,":[8],"including":[9],"e-commerce,":[10],"there":[11],"is":[12],"a":[13,30,49,90],"need":[14],"to":[15,63,67,85,104],"provide":[16],"additional":[17],"hardware":[18,32,46],"support":[19],"securing":[21],"information":[22],"from":[23],"memory":[24,39],"based":[25,51],"attacks.":[26,40],"This":[27],"work":[28],"presents":[29],"unified":[31],"framework":[33,47],"handling":[35],"spatial":[36],"and":[37,122],"temporal":[38],"The":[41,95],"paper":[42],"integrates":[43],"the":[44,73,76,87,99,110,131,136],"proposed":[45,77,96],"with":[48,53,109],"RISC-V":[50],"micro-architecture":[52],"an":[54,115,127],"enhanced":[55],"application":[56],"binary":[57],"interface":[58],"that":[59],"enables":[60],"software":[61],"layers":[62],"use":[64],"these":[65],"features":[66],"protect":[68],"data.":[70],"We":[71],"demonstrate":[72],"effectiveness":[74],"scheme":[78],"through":[79,89],"practical":[80],"case":[81],"studies":[82],"in":[83,107],"addition":[84],"taking":[86],"design":[88,93],"VLSI":[91],"CAD":[92],"flow.":[94],"processor":[97],"reduces":[98],"metadata":[100],"storage":[101],"overhead":[102,117],"up":[103],"4":[105],"x":[106],"comparison":[108],"existing":[111],"solutions,":[112],"while":[113],"incurring":[114],"area":[116],"just":[119],"1914":[120],"LUTs":[121],"2197":[123],"flip":[124],"flops":[125],"on":[126],"FPGA,":[128],"without":[129],"affecting":[130],"critical":[132],"path":[133],"delay":[134],"processor.":[137]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":7}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2017-06-30T00:00:00"}
