{"id":"https://openalex.org/W2626142696","doi":"https://doi.org/10.1145/3061639.3062327","title":"Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation","display_name":"Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation","publication_year":2017,"publication_date":"2017-06-13","ids":{"openalex":"https://openalex.org/W2626142696","doi":"https://doi.org/10.1145/3061639.3062327","mag":"2626142696"},"language":"en","primary_location":{"id":"doi:10.1145/3061639.3062327","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053628160","display_name":"Ioannis Seitanidis","orcid":"https://orcid.org/0000-0002-9693-0135"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Ioannis Seitanidis","raw_affiliation_strings":["Democritus University of Trace, ECE Dept., Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Democritus University of Trace, ECE Dept., Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074704256","display_name":"Giorgos Dimitrakopoulos","orcid":"https://orcid.org/0000-0003-3688-7865"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Giorgos Dimitrakopoulos","raw_affiliation_strings":["Democritus University of Trace, ECE Dept., Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Democritus University of Trace, ECE Dept., Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067917827","display_name":"Pavlos M. Mattheakis","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138743","display_name":"Siemens (France)","ror":"https://ror.org/04q9w3z30","country_code":"FR","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210138743"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pavlos Mattheakis","raw_affiliation_strings":["A Siemens Business, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"A Siemens Business, Grenoble, France","institution_ids":["https://openalex.org/I4210138743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5096875050","display_name":"Laurent Masse-Navete","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138743","display_name":"Siemens (France)","ror":"https://ror.org/04q9w3z30","country_code":"FR","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210138743"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Laurent Masse-Navete","raw_affiliation_strings":["A Siemens Business, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"A Siemens Business, Grenoble, France","institution_ids":["https://openalex.org/I4210138743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037827043","display_name":"David Chinnery","orcid":"https://orcid.org/0000-0003-2693-439X"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Chinnery","raw_affiliation_strings":["A Siemens Business, Fremont, USA"],"affiliations":[{"raw_affiliation_string":"A Siemens Business, Fremont, USA","institution_ids":["https://openalex.org/I4210137693"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5053628160"],"corresponding_institution_ids":["https://openalex.org/I147962203"],"apc_list":null,"apc_paid":null,"fwci":0.43,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.64364591,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6434454917907715},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5654386281967163},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.5354174971580505},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.5286096930503845},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.5188878178596497},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5056595802307129},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.45418089628219604},{"id":"https://openalex.org/keywords/composition","display_name":"Composition (language)","score":0.4424344003200531},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38874492049217224},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.25850531458854675},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1713988482952118}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6434454917907715},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5654386281967163},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.5354174971580505},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.5286096930503845},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.5188878178596497},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5056595802307129},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.45418089628219604},{"id":"https://openalex.org/C40231798","wikidata":"https://www.wikidata.org/wiki/Q1333743","display_name":"Composition (language)","level":2,"score":0.4424344003200531},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38874492049217224},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.25850531458854675},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1713988482952118},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3061639.3062327","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323220","display_name":"Alexander S. Onassis Public Benefit Foundation","ror":"https://ror.org/017nq0d63"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1921869937","https://openalex.org/W1966842574","https://openalex.org/W1980077563","https://openalex.org/W2011778848","https://openalex.org/W2012786899","https://openalex.org/W2063006063","https://openalex.org/W2070853264","https://openalex.org/W2073039296","https://openalex.org/W2095166045","https://openalex.org/W2116007667","https://openalex.org/W2171125334","https://openalex.org/W2177780683","https://openalex.org/W2404274178","https://openalex.org/W2533271602","https://openalex.org/W2535521862","https://openalex.org/W3161980919","https://openalex.org/W4245154887"],"related_works":["https://openalex.org/W4297672591","https://openalex.org/W4390073573","https://openalex.org/W2155935413","https://openalex.org/W2755854447","https://openalex.org/W2282591083","https://openalex.org/W3013232686","https://openalex.org/W2159458033","https://openalex.org/W1844463772","https://openalex.org/W2010347046","https://openalex.org/W1515086489"],"abstract_inverted_index":{"To":[0],"reduce":[1],"clock":[2,43,86],"power,":[3],"we":[4],"present":[5],"a":[6],"novel":[7],"timing-driven":[8],"incremental":[9],"multi-bit":[10],"register":[11,83],"(MBR)":[12],"composition":[13],"methodology":[14],"for":[15],"designs":[16],"that":[17,31],"may":[18],"be":[19,33,55],"rich":[20],"in":[21,77],"MBRs":[22],"after":[23],"logic":[24],"synthesis.":[25],"It":[26,80],"identifies":[27],"nearby":[28],"compatible":[29],"registers":[30,47,76],"can":[32,54],"merged":[34,49],"without":[35,39,88,94],"degrading":[36],"timing,":[37],"and":[38,85,93],"reducing":[40],"the":[41,51,59,72,78,96,100],"\"useful":[42],"skew\"":[44],"potential.":[45],"These":[46],"are":[48],"providing":[50],"MBR":[52],"placement":[53],"legalized":[56],"according":[57],"to":[58],"proposed":[60],"simplified":[61],"physical":[62],"constraints.":[63],"A":[64],"new":[65],"integer":[66],"linear":[67],"programming":[68],"(ILP)":[69],"formulation":[70],"minimizes":[71],"total":[73,97],"number":[74],"of":[75,99],"design.":[79],"significantly":[81],"reduces":[82],"count":[84],"capacitance,":[87],"adding":[89],"any":[90],"timing/routing/placement":[91],"violations":[92],"increasing":[95],"wire-length":[98],"designs,":[101],"as":[102],"shown":[103],"by":[104],"experimental":[105],"results":[106],"on":[107],"industrial":[108],"benchmarks.":[109]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
