{"id":"https://openalex.org/W2625704947","doi":"https://doi.org/10.1145/3061639.3062321","title":"Streak","display_name":"Streak","publication_year":2017,"publication_date":"2017-06-13","ids":{"openalex":"https://openalex.org/W2625704947","doi":"https://doi.org/10.1145/3061639.3062321","mag":"2625704947"},"language":"en","primary_location":{"id":"doi:10.1145/3061639.3062321","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062321","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101424523","display_name":"Derong Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Derong Liu","raw_affiliation_strings":["University of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089389140","display_name":"Vinicius Livramento","orcid":"https://orcid.org/0000-0001-5167-6359"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vinicius Livramento","raw_affiliation_strings":["Federal University of Santa Catarina, Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Santa Catarina, Brazil","institution_ids":["https://openalex.org/I4104125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100968137","display_name":"Salim Chowdhury","orcid":null},"institutions":[{"id":"https://openalex.org/I1342911587","display_name":"Oracle (United States)","ror":"https://ror.org/006c77m33","country_code":"US","type":"company","lineage":["https://openalex.org/I1342911587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Salim Chowdhury","raw_affiliation_strings":["Oracle Corp., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Oracle Corp., Austin, TX, USA","institution_ids":["https://openalex.org/I1342911587"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110183841","display_name":"Duo Ding","orcid":null},"institutions":[{"id":"https://openalex.org/I1342911587","display_name":"Oracle (United States)","ror":"https://ror.org/006c77m33","country_code":"US","type":"company","lineage":["https://openalex.org/I1342911587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Duo Ding","raw_affiliation_strings":["Oracle Corp., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Oracle Corp., Austin, TX, USA","institution_ids":["https://openalex.org/I1342911587"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064720873","display_name":"Huy T. Vo","orcid":"https://orcid.org/0000-0002-5963-6615"},"institutions":[{"id":"https://openalex.org/I1342911587","display_name":"Oracle (United States)","ror":"https://ror.org/006c77m33","country_code":"US","type":"company","lineage":["https://openalex.org/I1342911587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Huy Vo","raw_affiliation_strings":["Oracle Corp., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Oracle Corp., Austin, TX, USA","institution_ids":["https://openalex.org/I1342911587"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102963360","display_name":"Akshay Sharma","orcid":"https://orcid.org/0000-0003-4896-8726"},"institutions":[{"id":"https://openalex.org/I1342911587","display_name":"Oracle (United States)","ror":"https://ror.org/006c77m33","country_code":"US","type":"company","lineage":["https://openalex.org/I1342911587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Akshay Sharma","raw_affiliation_strings":["Oracle Corp., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Oracle Corp., Austin, TX, USA","institution_ids":["https://openalex.org/I1342911587"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["University of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5101424523"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.43,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64352153,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7664523124694824},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7221354842185974},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.678534984588623},{"id":"https://openalex.org/keywords/streak","display_name":"Streak","score":0.5874157547950745},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4941239655017853},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.47373640537261963},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4665876030921936},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38041722774505615},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32037490606307983},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18684563040733337},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17307543754577637},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14640897512435913}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7664523124694824},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7221354842185974},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.678534984588623},{"id":"https://openalex.org/C65185188","wikidata":"https://www.wikidata.org/wiki/Q107775","display_name":"Streak","level":2,"score":0.5874157547950745},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4941239655017853},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.47373640537261963},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4665876030921936},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38041722774505615},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32037490606307983},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18684563040733337},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17307543754577637},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14640897512435913},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3061639.3062321","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062321","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322942","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W2013245378","https://openalex.org/W2018082951","https://openalex.org/W2022129139","https://openalex.org/W2039267918","https://openalex.org/W2058646559","https://openalex.org/W2096423579","https://openalex.org/W2125232865","https://openalex.org/W2125831674","https://openalex.org/W2133679891","https://openalex.org/W2136532127","https://openalex.org/W2140055763","https://openalex.org/W2144733697","https://openalex.org/W2147708520","https://openalex.org/W2342679249","https://openalex.org/W2344800857","https://openalex.org/W2400313174","https://openalex.org/W2576595683","https://openalex.org/W4233613151","https://openalex.org/W6665108202","https://openalex.org/W6674680849","https://openalex.org/W6679784467","https://openalex.org/W6681251239"],"related_works":["https://openalex.org/W2082818786","https://openalex.org/W2000740899","https://openalex.org/W2371834895","https://openalex.org/W2997637732","https://openalex.org/W2381571063","https://openalex.org/W213647845","https://openalex.org/W2047678803","https://openalex.org/W2362555026","https://openalex.org/W4205718258","https://openalex.org/W1989674257"],"abstract_inverted_index":{"As":[0],"VLSI":[1],"technology":[2],"scales":[3],"to":[4],"deep":[5],"sub-micron,":[6],"design":[7,105],"for":[8,29],"interconnections":[9],"becomes":[10],"increasingly":[11],"challenging.":[12],"The":[13],"traditional":[14],"bus":[15],"routing":[16,100],"follows":[17],"a":[18,54,76,96],"sequential":[19],"bit-by-bit":[20],"order,":[21],"and":[22,50,59,104],"few":[23],"works":[24],"explicitly":[25],"target":[26],"inter-bit":[27],"regularity":[28],"signal":[30],"groups":[31,74],"via":[32],"multilayer":[33],"topology":[34,48],"selection.":[35],"To":[36],"overcome":[37],"these":[38],"limitations,":[39],"we":[40],"present":[41],"Streak,":[42],"an":[43,69],"efficient":[44],"framework":[45],"that":[46],"combines":[47],"generation":[49],"wire":[51,102],"synthesis":[52],"with":[53,81],"global":[55],"view":[56],"of":[57,78,115],"optimization":[58],"constrained":[60],"metal":[61],"layer":[62],"track":[63],"resource":[64],"allocation.":[65],"In":[66],"the":[67,82,90,99,113,116],"framework,":[68],"identification":[70],"stage":[71],"decomposes":[72],"binding":[73],"into":[75],"set":[77],"representative":[79],"objects;":[80],"generated":[83],"backbones,":[84],"equivalent":[85],"topologies":[86],"are":[87],"accompanied":[88],"by":[89],"bits":[91],"in":[92],"every":[93],"object;":[94],"then":[95],"formulation":[97],"guides":[98],"considering":[101],"congestion":[103],"regularity.":[106],"Experimental":[107],"results":[108],"using":[109],"industrial":[110],"benchmarks":[111],"demonstrate":[112],"effectiveness":[114],"proposed":[117],"technique.":[118]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2017-06-23T00:00:00"}
