{"id":"https://openalex.org/W2626482350","doi":"https://doi.org/10.1145/3061639.3062279","title":"LSC","display_name":"LSC","publication_year":2017,"publication_date":"2017-06-13","ids":{"openalex":"https://openalex.org/W2626482350","doi":"https://doi.org/10.1145/3061639.3062279","mag":"2626482350"},"language":"en","primary_location":{"id":"doi:10.1145/3061639.3062279","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049203311","display_name":"Love Singhal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Love Singhal","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044099321","display_name":"Mahesh A. Iyer","orcid":"https://orcid.org/0000-0002-1045-0019"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mahesh A. Iyer","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068392026","display_name":"Saurabh Adya","orcid":"https://orcid.org/0009-0000-4533-6577"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saurabh Adya","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5049203311"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.43,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.64371962,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7996898889541626},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7608267068862915},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.7352612614631653},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6222730278968811},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5287173390388489},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.493809312582016},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4934662878513336},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46491771936416626},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4479953646659851},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4454197585582733},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3501320779323578},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.28740811347961426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2356787621974945},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1701328456401825}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7996898889541626},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7608267068862915},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.7352612614631653},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6222730278968811},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5287173390388489},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.493809312582016},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4934662878513336},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46491771936416626},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4479953646659851},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4454197585582733},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3501320779323578},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.28740811347961426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2356787621974945},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1701328456401825},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3061639.3062279","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1977850862","https://openalex.org/W1991576731","https://openalex.org/W2002641171","https://openalex.org/W2020549672","https://openalex.org/W2029541370","https://openalex.org/W2068115726","https://openalex.org/W2083637347","https://openalex.org/W2090317622","https://openalex.org/W2111756578","https://openalex.org/W2139637699","https://openalex.org/W2141523221","https://openalex.org/W2169528473","https://openalex.org/W2170616854","https://openalex.org/W2533722497","https://openalex.org/W2538165366"],"related_works":["https://openalex.org/W2091330445","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W3147061323","https://openalex.org/W2004325343","https://openalex.org/W2138022277","https://openalex.org/W1631753024","https://openalex.org/W2533212402","https://openalex.org/W1984298705"],"abstract_inverted_index":{"With":[0],"recent":[1],"advances":[2],"in":[3,58,139,163,170],"Field":[4],"Programmable":[5],"Gate":[6],"Array":[7,50],"(FPGA)":[8],"architecture":[9],"and":[10,14,37,48,73,125,168,190],"design,":[11],"the":[12,29,59,69,75,127,134,140,158,176,186,206],"robustness":[13],"scalability":[15],"of":[16,77,104,123,129,166,197],"design":[17,65],"implementation":[18,27,85],"tools":[19,86],"is":[20,54,115,133,183,201],"becoming":[21],"increasingly":[22],"important.":[23],"In":[24,142],"an":[25,95],"FPGA":[26,71,84,150],"flow,":[28],"basic":[30],"logic":[31,45],"elements":[32],"(BLEs)":[33],"like":[34],"flip-flops":[35],"(FFs)":[36],"lookup":[38],"tables":[39],"(LUTs)":[40],"are":[41,81],"clustered":[42],"into":[43],"adaptive":[44],"modules":[46],"(ALMs)":[47],"Logic":[49],"Blocks":[51],"(LABs).":[52],"Clustering":[53],"a":[55,64,101,108],"key":[56],"stage":[57],"flow":[60],"that":[61],"determines":[62],"whether":[63,74],"can":[66],"fit":[67],"onto":[68],"target":[70,178],"device,":[72],"Quality":[76],"Results":[78],"(QoR)":[79],"goals":[80],"met.":[82],"Traditionally,":[83],"have":[87],"used":[88],"greedy":[89],"clustering":[90,97,137,160,208],"techniques.":[91],"This":[92],"paper":[93],"presents":[94],"innovative":[96],"algorithm":[98,114,138],"based":[99],"on":[100,152,185],"new":[102,159,207],"concept":[103],"consensus":[105],"building":[106],"at":[107],"large":[109],"scale":[110],"(LSC).":[111],"The":[112,193],"LSC":[113],"designed":[116],"to":[117,126],"work":[118],"with":[119,121,205],"designs":[120,145,200],"millions":[122],"elements,":[124],"best":[128],"our":[130,143],"knowledge,":[131],"this":[132],"first":[135],"parallel":[136],"industry.":[141],"industrial":[144],"benchmark":[146],"set":[147],"using":[148],"modern":[149],"devices":[151],"two":[153,177],"deep":[154],"submicron":[155],"technology":[156],"nodes,":[157],"engine":[161],"results":[162],"average":[164,187],"improvements":[165],"0.5%":[167],"2.5%":[169],"maximum":[171],"clock":[172],"frequency":[173],"(Fmax)":[174],"for":[175],"devices.":[179],"Additionally,":[180],"wiring":[181],"usage":[182],"improved":[184,203],"by":[188],"2.8%":[189],"6.5%":[191],"respectively.":[192],"fitting":[194],"success":[195],"rate":[196],"highly":[198],"utilized":[199],"also":[202],"significantly":[204],"engine.":[209]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":5},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2017-06-23T00:00:00"}