{"id":"https://openalex.org/W2624772948","doi":"https://doi.org/10.1145/3061639.3062272","title":"Leave the Cache Hierarchy Operation as It Is","display_name":"Leave the Cache Hierarchy Operation as It Is","publication_year":2017,"publication_date":"2017-06-13","ids":{"openalex":"https://openalex.org/W2624772948","doi":"https://doi.org/10.1145/3061639.3062272","mag":"2624772948"},"language":"en","primary_location":{"id":"doi:10.1145/3061639.3062272","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062272","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024858702","display_name":"Chun-Hao Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chun-Hao Lai","raw_affiliation_strings":["National Taiwan University"],"affiliations":[{"raw_affiliation_string":"National Taiwan University","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077387335","display_name":"Jishen Zhao","orcid":"https://orcid.org/0000-0002-1969-743X"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jishen Zhao","raw_affiliation_strings":["University of California, Santa Cruz"],"affiliations":[{"raw_affiliation_string":"University of California, Santa Cruz","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046948316","display_name":"Chia-Lin Yang","orcid":"https://orcid.org/0000-0003-0091-5027"},"institutions":[{"id":"https://openalex.org/I84653119","display_name":"Academia Sinica","ror":"https://ror.org/05bxb3784","country_code":"TW","type":"facility","lineage":["https://openalex.org/I84653119"]},{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Lin Yang","raw_affiliation_strings":["National Taiwan University and Academia Sinica"],"affiliations":[{"raw_affiliation_string":"National Taiwan University and Academia Sinica","institution_ids":["https://openalex.org/I16733864","https://openalex.org/I84653119"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5024858702"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":1.8025,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86307894,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.8216580152511597},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7970514297485352},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7027677297592163},{"id":"https://openalex.org/keywords/persistent-data-structure","display_name":"Persistent data structure","score":0.5999025106430054},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5602418184280396},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.5327850580215454},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4651751220226288},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46454858779907227},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.4302843511104584},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.41262099146842957},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.41142815351486206},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.39365383982658386},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34353700280189514},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.30580586194992065},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.25610822439193726},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.11838030815124512},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.11479324102401733},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.1048930287361145},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.07437935471534729},{"id":"https://openalex.org/keywords/political-science","display_name":"Political science","score":0.06297671794891357}],"concepts":[{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.8216580152511597},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7970514297485352},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7027677297592163},{"id":"https://openalex.org/C888380","wikidata":"https://www.wikidata.org/wiki/Q2427787","display_name":"Persistent data structure","level":2,"score":0.5999025106430054},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5602418184280396},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.5327850580215454},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4651751220226288},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46454858779907227},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.4302843511104584},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.41262099146842957},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.41142815351486206},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.39365383982658386},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34353700280189514},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.30580586194992065},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.25610822439193726},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.11838030815124512},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.11479324102401733},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.1048930287361145},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.07437935471534729},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.06297671794891357},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3061639.3062272","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3061639.3062272","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 54th Annual Design Automation Conference 2017","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1522250664","https://openalex.org/W1965912002","https://openalex.org/W1992755462","https://openalex.org/W2005887179","https://openalex.org/W2102032581","https://openalex.org/W2108048675","https://openalex.org/W2113167168","https://openalex.org/W2113637091","https://openalex.org/W2138146350","https://openalex.org/W2146148582","https://openalex.org/W2150662965","https://openalex.org/W2151745115","https://openalex.org/W2157808045","https://openalex.org/W2162639668","https://openalex.org/W2197809502","https://openalex.org/W2220914167","https://openalex.org/W2234174598","https://openalex.org/W2316501305","https://openalex.org/W2318717892","https://openalex.org/W2406569785","https://openalex.org/W2565270815","https://openalex.org/W4233509008","https://openalex.org/W4241729479","https://openalex.org/W4244155122"],"related_works":["https://openalex.org/W2900563922","https://openalex.org/W2079019992","https://openalex.org/W3111801817","https://openalex.org/W1961903935","https://openalex.org/W4313496011","https://openalex.org/W2115782696","https://openalex.org/W2217292995","https://openalex.org/W2966447112","https://openalex.org/W109043737","https://openalex.org/W2624772948"],"abstract_inverted_index":{"Persistent":[0],"memory":[1,6],"places":[2],"NVRAM":[3,16],"on":[4],"the":[5],"bus,":[7],"offering":[8],"fast":[9],"access":[10],"to":[11,36],"persistent":[12],"data.":[13],"Yet":[14],"maintaining":[15],"data":[17],"persistence":[18],"raises":[19],"a":[20],"host":[21],"of":[22],"challenges.":[23],"Most":[24],"proposed":[25],"schemes":[26],"either":[27],"incur":[28],"much":[29],"performance":[30],"overhead":[31],"or":[32],"require":[33],"substantial":[34],"modifications":[35],"existing":[37],"architectures.":[38]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
