{"id":"https://openalex.org/W2578575989","doi":"https://doi.org/10.1145/3039902.3039907","title":"An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug","display_name":"An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug","publication_year":2017,"publication_date":"2017-01-11","ids":{"openalex":"https://openalex.org/W2578575989","doi":"https://doi.org/10.1145/3039902.3039907","mag":"2578575989"},"language":"en","primary_location":{"id":"doi:10.1145/3039902.3039907","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3039902.3039907","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064318448","display_name":"Fatemeh Eslami","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Fatemeh Eslami","raw_affiliation_strings":["University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J.E. Wilton","raw_affiliation_strings":["University of British Columbia, Vancouver, Canada"],"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5064318448"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.5734,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.67902241,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"44","issue":"4","first_page":"20","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8954453468322754},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.8428909778594971},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8093171715736389},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7638369798660278},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.7299373149871826},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6710894107818604},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.5729232430458069},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5198239088058472},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.46845316886901855},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4401966333389282},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3229180872440338},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07908394932746887}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8954453468322754},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.8428909778594971},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8093171715736389},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7638369798660278},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.7299373149871826},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6710894107818604},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.5729232430458069},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5198239088058472},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.46845316886901855},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4401966333389282},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3229180872440338},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07908394932746887},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3039902.3039907","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3039902.3039907","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1976150142","https://openalex.org/W2005602803","https://openalex.org/W2035057034","https://openalex.org/W2062513952","https://openalex.org/W2073321629","https://openalex.org/W2100580949","https://openalex.org/W2105993342","https://openalex.org/W2111945398","https://openalex.org/W2116433835","https://openalex.org/W2275304190","https://openalex.org/W2284193196"],"related_works":["https://openalex.org/W2361273971","https://openalex.org/W2351581202","https://openalex.org/W2978026406","https://openalex.org/W2385068581","https://openalex.org/W2381166695","https://openalex.org/W4241045879","https://openalex.org/W2366346238","https://openalex.org/W2388687068","https://openalex.org/W2366922255","https://openalex.org/W2993910401"],"abstract_inverted_index":{"Embedded":[0],"system":[1],"designers":[2],"can":[3,35],"benefit":[4],"from":[5],"FPGA":[6,46],"accelerators":[7],"to":[8,28,113,138,152,173],"achieve":[9],"higher":[10],"performance":[11],"and":[12,31,39,56,76,103,124,136,163,188],"efficiency.":[13],"However,":[14,61],"there":[15],"are":[16,80],"challenges":[17],"that":[18,184],"do":[19],"not":[20],"exist":[21],"in":[22,68,119,205,209],"software":[23,26],"development;":[24],"using":[25,181,185],"simulators":[27],"validate":[29],"large":[30],"complex":[32],"hardware":[33,69,73],"designs":[34,42],"be":[36],"extremely":[37],"slow":[38],"impractical.":[40],"Debugging":[41],"implemented":[43],"on":[44,157],"an":[45,195],"enables":[47],"running":[48],"the":[49,65,83,86,98,106,110,115,158,170,174,201],"design":[50,107],"at":[51,193],"speed":[52],"for":[53,100],"long":[54,120],"runs":[55],"more":[57],"exhaustive":[58],"test":[59],"cases.":[60],"limited":[62],"observability":[63],"is":[64,95,150,161,192],"primary":[66],"challenge":[67],"debug.":[70],"To":[71],"enhance":[72],"observability,":[74],"trace-buffers":[75,99],"a":[77,89,132,147,154,206],"trigger":[78,116,155,171],"circuitry":[79],"inserted":[81],"into":[82,97],"design.":[84],"During":[85],"device":[87],"operation,":[88],"history":[90],"of":[91,93,168,197],"signals":[92],"interest":[94],"recorded":[96],"off-line":[101],"debug":[102,121,143,210],"validation.":[104],"Recompiling":[105],"every":[108],"time":[109],"designer":[111],"wishes":[112],"modify":[114],"condition":[117],"results":[118],"turn-around":[122,211],"times":[123],"reduced":[125],"productivity.":[126],"In":[127],"this":[128],"work,":[129],"we":[130],"present":[131],"pre-synthesized":[133],"overlay":[134,175,187],"fabric":[135],"algorithm":[137,190],"enable":[139],"rapid":[140],"triggering;":[141],"during":[142],"turn-around,":[144],"TriggerPlus":[145,160],",":[146],"greedy":[148],"algorithm,":[149],"used":[151],"implement":[153],"circuit":[156,172],"overlay.":[159],"fast":[162],"simple,":[164],"yet":[165],"still":[166],"capable":[167],"mapping":[169,189],"fabric.":[176],"We":[177],"evaluate":[178],"our":[179,186],"techniques":[180],"VPR,":[182],"showing":[183],"together":[191],"least":[194],"order":[196],"magnitude":[198],"faster":[199],"than":[200],"previous":[202],"work":[203],"resulting":[204],"significant":[207],"reduction":[208],"times.":[212]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
