{"id":"https://openalex.org/W2604701890","doi":"https://doi.org/10.1145/3036669.3041226","title":"Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform","display_name":"Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform","publication_year":2017,"publication_date":"2017-03-15","ids":{"openalex":"https://openalex.org/W2604701890","doi":"https://doi.org/10.1145/3036669.3041226","mag":"2604701890"},"language":"en","primary_location":{"id":"doi:10.1145/3036669.3041226","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3036669.3041226","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010411820","display_name":"I. Bolsens","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ivo Bolsens","raw_affiliation_strings":["Xinlinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xinlinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5010411820"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"23","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8129228353500366},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6216954588890076},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5912238955497742},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.5196112990379333},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.497974157333374},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4660426676273346},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46053221821784973},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.43789204955101013},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4289221465587616},{"id":"https://openalex.org/keywords/moores-law","display_name":"Moore's law","score":0.41866210103034973},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.41259440779685974},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.3326473832130432},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29878681898117065},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.20490628480911255},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20472779870033264},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.18648046255111694},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09714904427528381}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8129228353500366},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6216954588890076},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5912238955497742},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.5196112990379333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.497974157333374},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4660426676273346},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46053221821784973},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.43789204955101013},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4289221465587616},{"id":"https://openalex.org/C206891323","wikidata":"https://www.wikidata.org/wiki/Q178655","display_name":"Moore's law","level":2,"score":0.41866210103034973},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.41259440779685974},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.3326473832130432},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29878681898117065},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.20490628480911255},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20472779870033264},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.18648046255111694},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09714904427528381},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3036669.3041226","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3036669.3041226","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2424214691","https://openalex.org/W2418552007","https://openalex.org/W2768229929","https://openalex.org/W2805193191","https://openalex.org/W3139819943","https://openalex.org/W3047339307","https://openalex.org/W2050402383"],"abstract_inverted_index":{"Since":[0],"their":[1,8],"inception,":[2],"FPGAs":[3],"have":[4],"changed":[5],"significantly":[6],"in":[7,23,65,74,97],"capacity":[9],"and":[10,29,76,81],"architecture.":[11],"The":[12,38],"devices":[13,34,70],"we":[14],"use":[15],"today":[16],"are":[17,83],"called":[18],"upon":[19],"to":[20,72,94,99],"solve":[21],"problems":[22],"mixed-signal,":[24],"high-speed":[25],"communications,":[26],"signal":[27],"processing":[28],"compute":[30],"acceleration":[31],"that":[32,47,92],"early":[33],"could":[35],"not":[36],"address.":[37],"architecture":[39],"has":[40],"evolved":[41],"towards":[42],"an":[43],"\"All":[44],"Programmable\"":[45],"platform":[46],"immerses":[48],"multiple":[49,63],"programmable":[50],"technologies":[51],"into":[52],"a":[53],"complex":[54],"interconnect":[55],"infrastructure":[56],"that,":[57],"today,":[58],"spans":[59],"the":[60,69,102],"boundary":[61,103],"of":[62,104],"dies":[64],"one":[66],"package.":[67],"As":[68],"continue":[71,100],"grow":[73],"capability":[75],"complexity,":[77],"new":[78],"design":[79],"tools":[80],"methodologies":[82],"being":[84],"proposed.":[85],"We":[86],"will":[87],"discuss":[88],"future":[89],"technology":[90],"challenges":[91],"need":[93],"be":[95],"solved":[96],"order":[98],"pushing":[101],"integration.":[105]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
