{"id":"https://openalex.org/W2595334824","doi":"https://doi.org/10.1145/3036669.3038241","title":"Clock-Aware FPGA Placement Contest","display_name":"Clock-Aware FPGA Placement Contest","publication_year":2017,"publication_date":"2017-03-15","ids":{"openalex":"https://openalex.org/W2595334824","doi":"https://doi.org/10.1145/3036669.3038241","mag":"2595334824"},"language":"en","primary_location":{"id":"doi:10.1145/3036669.3038241","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3036669.3038241","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066133332","display_name":"Stephen Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Stephen Yang","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022588908","display_name":"Chandra Mulpuri","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chandra Mulpuri","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017844381","display_name":"G. Sudhaamsh Mohan Reddy","orcid":"https://orcid.org/0000-0002-3828-5852"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sainath Reddy","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030529234","display_name":"Meghraj Kalase","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Meghraj Kalase","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046755128","display_name":"Srinivasan Dasasathyan","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srinivasan Dasasathyan","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069832936","display_name":"Mehrdad Eslami Dehkordi","orcid":"https://orcid.org/0000-0001-7663-4059"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mehrdad E. Dehkordi","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014266034","display_name":"Marvin Tom","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marvin Tom","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021268829","display_name":"Rajat Aggarwal","orcid":"https://orcid.org/0000-0001-7131-5294"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajat Aggarwal","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5066133332"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":1.4614,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.82958719,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8877315521240234},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.711891770362854},{"id":"https://openalex.org/keywords/contest","display_name":"CONTEST","score":0.6723417639732361},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5947344899177551},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5590885877609253},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5176092386245728},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48557135462760925},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.468507319688797},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4529591202735901},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.43615010380744934},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33266177773475647},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.17768985033035278},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.11703747510910034},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06850802898406982},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06242555379867554}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8877315521240234},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.711891770362854},{"id":"https://openalex.org/C2777582232","wikidata":"https://www.wikidata.org/wiki/Q5013414","display_name":"CONTEST","level":2,"score":0.6723417639732361},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5947344899177551},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5590885877609253},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5176092386245728},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48557135462760925},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.468507319688797},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4529591202735901},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.43615010380744934},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33266177773475647},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.17768985033035278},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.11703747510910034},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06850802898406982},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06242555379867554},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3036669.3038241","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3036669.3038241","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2037266728","https://openalex.org/W2328615082","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2536774307","https://openalex.org/W2538165366","https://openalex.org/W4323927861"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2164041287","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309","https://openalex.org/W272033699","https://openalex.org/W2091330445"],"abstract_inverted_index":{"Modern":[0],"FPGA":[1,10,16,20,53,60,65],"device":[2],"contains":[3],"complex":[4],"clocking":[5,17,30],"architecture":[6,31],"on":[7,84],"top":[8],"of":[9,48],"logic":[11],"fabric.":[12],"To":[13],"best":[14,34],"utilize":[15],"architecture,":[18],"both":[19],"designers":[21],"and":[22,32,42,63],"EDA":[23],"tool":[24],"developers":[25],"need":[26,91],"to":[27,92,99],"understand":[28],"the":[29,49,102],"design":[33,38,54,61,93],"methodology/algorithm":[35],"for":[36],"various":[37],"styles.":[39],"Clock":[40],"legalization":[41,74],"clock":[43,73,95],"aware":[44,96],"placement":[45,66,97],"become":[46],"one":[47],"key":[50],"factors":[51],"in":[52,101],"flow.":[55],"They":[56],"can":[57,68],"greatly":[58],"influence":[59],"performance":[62],"routability.":[64],"problem":[67],"get":[69],"very":[70],"difficult":[71],"with":[72],"constraints.":[75],"This":[76],"year's":[77,86],"contest":[78],"is":[79],"a":[80],"continuous":[81],"challenge":[82],"based":[83],"last":[85],"routability":[87],"driven":[88],"placement.":[89],"Contestants":[90],"best-in-class":[94],"approach":[98],"excel":[100],"contest.":[103]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3}],"updated_date":"2026-05-04T08:30:34.212998","created_date":"2025-10-10T00:00:00"}