{"id":"https://openalex.org/W2605004571","doi":"https://doi.org/10.1145/3036669.3036671","title":"Clock Tree Construction based on Arrival Time Constraints","display_name":"Clock Tree Construction based on Arrival Time Constraints","publication_year":2017,"publication_date":"2017-03-15","ids":{"openalex":"https://openalex.org/W2605004571","doi":"https://doi.org/10.1145/3036669.3036671","mag":"2605004571"},"language":"en","primary_location":{"id":"doi:10.1145/3036669.3036671","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3036669.3036671","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=3036671&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://dl.acm.org/ft_gateway.cfm?id=3036671&type=pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014892277","display_name":"Rickard Ewetz","orcid":"https://orcid.org/0000-0002-4183-6926"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rickard Ewetz","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"67","last_page":"74"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7811387777328491},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7003034353256226},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.63795006275177},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6310344934463501},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6156383752822876},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5693946480751038},{"id":"https://openalex.org/keywords/arrival-time","display_name":"Arrival time","score":0.5240445733070374},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5007486343383789},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4869295358657837},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4158332943916321},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3449555039405823},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.33680957555770874},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15914657711982727},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12430235743522644},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08280101418495178},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.07120338082313538},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.06975346803665161}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7811387777328491},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7003034353256226},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.63795006275177},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6310344934463501},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6156383752822876},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5693946480751038},{"id":"https://openalex.org/C3017552255","wikidata":"https://www.wikidata.org/wiki/Q4135208","display_name":"Arrival time","level":2,"score":0.5240445733070374},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5007486343383789},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4869295358657837},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4158332943916321},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3449555039405823},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.33680957555770874},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15914657711982727},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12430235743522644},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08280101418495178},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.07120338082313538},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.06975346803665161},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C22212356","wikidata":"https://www.wikidata.org/wiki/Q775325","display_name":"Transport engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3036669.3036671","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3036669.3036671","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=3036671&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"},{"id":"pmh:oai:stars.library.ucf.edu:scopus2015-8496","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2015/7497","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2015-2019","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/3036669.3036671","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3036669.3036671","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=3036671&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2017 ACM on International Symposium on Physical Design","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2692225030","display_name":"SHF:  Small:  Synthesis of Robust Clock Networks for Multiple-Corner Multiple-Mode Designs","funder_award_id":"1527562","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6787993161","display_name":"SHF: Medium: Say \"No\" to Extraction--A Transformative Circuit Simulation Paradigm Guided by First Principles","funder_award_id":"1065318","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G8753606650","display_name":null,"funder_award_id":"CCF-1527562 and CCF-1065318","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320309036","display_name":"Purdue University","ror":"https://ror.org/02dqehb95"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2605004571.pdf","grobid_xml":"https://content.openalex.org/works/W2605004571.grobid-xml"},"referenced_works_count":21,"referenced_works":["https://openalex.org/W1983206124","https://openalex.org/W2011778848","https://openalex.org/W2014965059","https://openalex.org/W2029522775","https://openalex.org/W2034653499","https://openalex.org/W2041950850","https://openalex.org/W2060463852","https://openalex.org/W2113682107","https://openalex.org/W2120116751","https://openalex.org/W2128237591","https://openalex.org/W2148609278","https://openalex.org/W2155911206","https://openalex.org/W2180955215","https://openalex.org/W2293567771","https://openalex.org/W2333469681","https://openalex.org/W2510949177","https://openalex.org/W2955479062","https://openalex.org/W4230442644","https://openalex.org/W4237096326","https://openalex.org/W4246946013","https://openalex.org/W4254506919"],"related_works":["https://openalex.org/W2116259070","https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W3201048403","https://openalex.org/W2123512677","https://openalex.org/W4232019485","https://openalex.org/W2144282137","https://openalex.org/W2891365107","https://openalex.org/W4327499872","https://openalex.org/W2032549010"],"abstract_inverted_index":{"There":[0],"are":[1,36,51,54,116,133],"striking":[2],"differences":[3],"between":[4,99],"constructing":[5],"clock":[6,120,147,159,169],"trees":[7,121,160,170],"based":[8,15,172],"on":[9,16,173],"dynamic":[10,174],"implied":[11,22,175],"skew":[12,23,124,176],"constraints":[13,24,35,50,62,83,115,132],"and":[14,53,102,135],"static":[17,47,112],"arrival":[18,48,81,113],"time":[19,43,49,82,114],"constraints.":[20,177],"Dynamic":[21],"allow":[25,86],"the":[26,34,61,71,78,87,109,131,138,142,145,154],"full":[27,88],"timing":[28,89,103],"margins":[29,90],"to":[30,38,57,91,118],"be":[31,39,58,64,92],"utilized,":[32],"but":[33],"required":[37,56],"updated":[40],"(with":[41],"high":[42],"complexity).":[44],"In":[45,106],"contrast,":[46],"decoupled":[52],"not":[55,85],"updated.":[59],"Therefore,":[60],"can":[63],"obtained":[65],"in":[66,158],"constant":[67],"time,":[68],"which":[69],"facilitates":[70],"exploration":[72,101],"of":[73,111,144],"various":[74,127],"tree":[75,128],"topologies.":[76,129],"On":[77],"other":[79],"hand,":[80],"do":[84],"utilized.":[93],"Consequently,":[94],"there":[95],"is":[96,150],"a":[97],"tradeoff":[98],"topology":[100],"margin":[104],"utilization.":[105],"this":[107],"paper,":[108],"advantages":[110],"leveraged":[117],"construct":[119],"with":[122,161,168],"useful":[123],"while":[125],"exploring":[126],"Moreover,":[130],"specified":[134],"respecified":[136],"throughout":[137],"synthesis":[139],"process":[140],"reduce":[141],"cost":[143,166],"constructed":[146,171],"trees.":[148],"It":[149],"experimentally":[151],"demonstrated":[152],"that":[153],"proposed":[155],"approach":[156],"results":[157],"16%":[162],"lower":[163],"average":[164],"capacitive":[165],"compared":[167]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}