{"id":"https://openalex.org/W2601686331","doi":"https://doi.org/10.1145/3009971","title":"(FPL 2015) Scavenger","display_name":"(FPL 2015) Scavenger","publication_year":2017,"publication_date":"2017-03-22","ids":{"openalex":"https://openalex.org/W2601686331","doi":"https://doi.org/10.1145/3009971","mag":"2601686331"},"language":"en","primary_location":{"id":"doi:10.1145/3009971","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3009971","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101767631","display_name":"Hsin-Jung Yang","orcid":"https://orcid.org/0000-0002-0990-7763"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hsin-Jung Yang","raw_affiliation_strings":["CSAIL, Massachusetts Institute of Technology, Cambridge, USA"],"raw_orcid":"https://orcid.org/0000-0002-0990-7763","affiliations":[{"raw_affiliation_string":"CSAIL, Massachusetts Institute of Technology, Cambridge, USA","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027505039","display_name":"Kermin Fleming","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kermin Fleming","raw_affiliation_strings":["SSG, Intel Corporation, Hudson, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SSG, Intel Corporation, Hudson, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000955555","display_name":"Felix Winterstein","orcid":"https://orcid.org/0000-0002-2525-0693"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Felix Winterstein","raw_affiliation_strings":["CAS, Imperial College London, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAS, Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109306000","display_name":"Michael Adler","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Adler","raw_affiliation_strings":["SSG, Intel Corporation, Hudson, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SSG, Intel Corporation, Hudson, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel Emer","raw_affiliation_strings":["CSAIL, Massachusetts Institute of Technology, Cambridge, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSAIL, Massachusetts Institute of Technology, Cambridge, USA","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3422,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.8114547,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"10","issue":"2","first_page":"1","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8998621702194214},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5933533906936646},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5791159272193909},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5156027674674988},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4722031056880951},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4425984025001526},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4281325340270996},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.42723894119262695},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4238664507865906},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4178411364555359},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.365225613117218},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.35051125288009644},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.22269734740257263},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22065094113349915},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.16072991490364075}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8998621702194214},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5933533906936646},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5791159272193909},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5156027674674988},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4722031056880951},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4425984025001526},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4281325340270996},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.42723894119262695},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4238664507865906},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4178411364555359},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.365225613117218},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.35051125288009644},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.22269734740257263},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22065094113349915},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.16072991490364075}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3009971","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3009971","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1963756414","https://openalex.org/W1970032753","https://openalex.org/W1988132189","https://openalex.org/W1992491248","https://openalex.org/W1999489580","https://openalex.org/W2013594929","https://openalex.org/W2022128349","https://openalex.org/W2026307700","https://openalex.org/W2036525499","https://openalex.org/W2080380374","https://openalex.org/W2093994565","https://openalex.org/W2094966716","https://openalex.org/W2095643031","https://openalex.org/W2097537332","https://openalex.org/W2111154193","https://openalex.org/W2112678088","https://openalex.org/W2121711421","https://openalex.org/W2126372249","https://openalex.org/W2127699991","https://openalex.org/W2137385009","https://openalex.org/W2161160262","https://openalex.org/W2162113220","https://openalex.org/W2166029537","https://openalex.org/W2604383488","https://openalex.org/W3157778366","https://openalex.org/W4242953705"],"related_works":["https://openalex.org/W2132808802","https://openalex.org/W2145523143","https://openalex.org/W3091730480","https://openalex.org/W2950074507","https://openalex.org/W2350803493","https://openalex.org/W15724499","https://openalex.org/W2126827366","https://openalex.org/W2528635421","https://openalex.org/W5673888","https://openalex.org/W2174898847"],"abstract_inverted_index":{"High-level":[0],"abstractions":[1],"separate":[2],"algorithm":[3],"design":[4,58,171],"from":[5],"platform":[6,30,95],"implementation,":[7],"allowing":[8],"programmers":[9,23],"to":[10,28,44,73,93,114,166,191,212],"focus":[11],"on":[12,32,98,198],"algorithms":[13],"while":[14],"building":[15],"complex":[16],"systems.":[17],"This":[18],"separation":[19],"also":[20,120],"provides":[21],"system":[22],"and":[24,63,118],"compilers":[25],"an":[26,33,122],"opportunity":[27],"optimize":[29],"services":[31],"application-by-application":[34],"basis.":[35],"In":[36,104],"field-programmable":[37],"gate":[38],"arrays":[39],"(FPGAs),":[40],"platform-level":[41],"malleability":[42],"extends":[43],"the":[45,60,94,101,129,201,207,213],"memory":[46,53,67,85,88,134,146,168],"system:":[47],"Unlike":[48],"general-purpose":[49],"processors,":[50],"in":[51,156],"which":[52,110],"hardware":[54],"is":[55],"fixed":[56],"at":[57],"time,":[59],"capacity,":[61],"associativity,":[62],"topology":[64],"of":[65,100,125,131,179,189,209],"FPGA":[66],"systems":[68],"may":[69,80,90,148],"all":[70,145],"be":[71,91,141],"tuned":[72],"improve":[74],"application":[75,78],"performance.":[76],"Since":[77],"kernels":[79],"only":[81],"explicitly":[82],"use":[83,97],"few":[84],"resources,":[86],"substantial":[87],"capacity":[89],"available":[92],"for":[96,127,170],"behalf":[99],"user":[102],"program.":[103],"this":[105],"work,":[106],"we":[107,119,162],"present":[108],"Scavenger,":[109],"utilizes":[111],"spare":[112,138],"resources":[113,139,147],"construct":[115],"program-optimized":[116],"memories,":[117],"perform":[121],"initial":[123],"exploration":[124],"methods":[126],"automating":[128],"construction":[130],"these":[132],"application-specific":[133],"hierarchies.":[135],"Although":[136],"exploiting":[137],"can":[140],"beneficial,":[142],"na\u00efvely":[143],"consuming":[144],"cause":[149],"frequency":[150],"degradation.":[151],"To":[152],"relieve":[153],"timing":[154],"pressure":[155],"large":[157],"block":[158],"RAM":[159],"(BRAM)":[160],"structures,":[161],"provide":[163],"microarchitectural":[164],"techniques":[165],"trade":[167],"latency":[169],"frequency.":[172],"We":[173],"demonstrate,":[174],"by":[175],"examining":[176],"a":[177,194],"set":[178],"benchmarks,":[180],"that":[181],"our":[182],"scalable":[183],"cache":[184,203],"microarchitecture":[185,204],"achieves":[186],"performance":[187],"gains":[188],"7%":[190],"74%":[192],"(with":[193],"26%":[195],"geometric":[196],"mean":[197],"average)":[199],"over":[200],"baseline":[202],"when":[205],"scaling":[206],"size":[208],"first-level":[210],"caches":[211],"maximum.":[214]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}