{"id":"https://openalex.org/W2558337280","doi":"https://doi.org/10.1145/2990299.2990317","title":"Inter-FPGA routing environment for performance exploration of multi-FPGA systems","display_name":"Inter-FPGA routing environment for performance exploration of multi-FPGA systems","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2558337280","doi":"https://doi.org/10.1145/2990299.2990317","mag":"2558337280"},"language":"en","primary_location":{"id":"doi:10.1145/2990299.2990317","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2990299.2990317","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088890905","display_name":"Umer Farooq","orcid":"https://orcid.org/0000-0002-5220-4908"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Umer Farooq","raw_affiliation_strings":["Sorbonne Universit\u00e9s, UPMC University, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sorbonne Universit\u00e9s, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110226823","display_name":"Roselyne Chotin-Avot","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Roselyne Chotin-Avot","raw_affiliation_strings":["Sorbonne Universit\u00e9s, UPMC University, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sorbonne Universit\u00e9s, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030040379","display_name":"Muhammad Moazam Azeem","orcid":"https://orcid.org/0000-0002-1644-7240"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Moazam Azeem","raw_affiliation_strings":["Sorbonne Universit\u00e9s, UPMC University, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sorbonne Universit\u00e9s, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029631221","display_name":"Maminionja Ravoson","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Maminionja Ravoson","raw_affiliation_strings":["Sorbonne Universit\u00e9s, UPMC University, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sorbonne Universit\u00e9s, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019168974","display_name":"Mariem Turki","orcid":"https://orcid.org/0000-0003-2646-3962"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mariem Turki","raw_affiliation_strings":["Sorbonne Universit\u00e9s, UPMC University, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sorbonne Universit\u00e9s, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["Sorbonne Universit\u00e9s, UPMC University, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sorbonne Universit\u00e9s, UPMC University, Paris, France","institution_ids":["https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1161,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.81269909,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"107","last_page":"113"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9545644521713257},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7178194522857666},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6932405829429626},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.6426723003387451},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6261494159698486},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5709612965583801},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4291588068008423}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9545644521713257},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7178194522857666},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6932405829429626},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.6426723003387451},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6261494159698486},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5709612965583801},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4291588068008423},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2990299.2990317","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2990299.2990317","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W32337268","https://openalex.org/W1992578807","https://openalex.org/W2032699516","https://openalex.org/W2063519198","https://openalex.org/W2109907925","https://openalex.org/W2133712953","https://openalex.org/W2148658001","https://openalex.org/W2169528473","https://openalex.org/W2275304190","https://openalex.org/W2541314013","https://openalex.org/W4243872270"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2110265185","https://openalex.org/W2113648965","https://openalex.org/W2155484023","https://openalex.org/W4200391368","https://openalex.org/W2388221044","https://openalex.org/W2984236338","https://openalex.org/W2619213283","https://openalex.org/W3117064361","https://openalex.org/W2057745131"],"abstract_inverted_index":{"Multi-FPGA":[0],"platforms":[1],"are":[2,84,126,134,149],"a":[3,88,112],"popular":[4],"choice":[5],"today":[6],"for":[7,58,141],"complex":[8],"system":[9],"prototyping":[10,61],"because":[11],"they":[12],"offer":[13],"high":[14],"execution":[15],"speed,":[16],"low":[17],"cost,":[18],"and":[19,55,120],"real":[20],"world":[21],"testing":[22],"experience.":[23],"However,":[24],"performance":[25,46,110,118],"of":[26,78,95,97,99,105,111,130,167],"multi-FPGA":[27,59,155],"based":[28,60],"systems":[29],"is":[30,115],"severely":[31],"affected":[32],"by":[33],"widening":[34],"logic":[35],"to":[36,43,71,138,162,213],"I/O":[37],"gap":[38],"in":[39,48],"FPGAs.":[40],"In":[41],"order":[42],"address":[44],"the":[45,79,109,163],"issue,":[47],"this":[49],"work,":[50],"we":[51,195],"propose":[52],"an":[53,64],"exploration":[54,119],"optimization":[56],"flow":[57],"that":[62,154,182,202],"gives":[63,207],"end-to-end":[65],"experience":[66],"starting":[67],"from":[68,136],"benchmark":[69],"generation":[70],"optimized":[72],"inter-FPGA":[73,91,106,146,158],"routing.":[74],"Using":[75],"generic":[76,89],"tools":[77],"flow,":[80],"ten":[81],"large":[82],"benchmarks":[83,168],"generated.":[85],"Then,":[86],"through":[87],"novel":[90],"routing":[92],"environment,":[93],"effect":[94],"variation":[96],"number":[98,104,129],"FPGAs":[100,131,187,206],"as":[101,103,211],"well":[102],"tracks":[107,159],"on":[108,132,189],"target":[113],"design":[114],"explored.":[116],"For":[117],"optimization,":[121],"five":[122],"different":[123,145,179],"FPGA":[124,183,215],"boards":[125,156,180,216],"utilized":[127],"where":[128],"board":[133,143,184,203],"varied":[135],"two":[137],"six.":[139],"Moreover,":[140],"each":[142],"four":[144,205],"track":[147],"combinations":[148],"used.":[150],"Experimental":[151],"results":[152],"reveal":[153],"with":[157,185,204],"corresponding":[160],"optimally":[161],"cut":[164],"net":[165],"requirements":[166],"under":[169,217],"consideration":[170],"give":[171],"best":[172,191],"frequency":[173,176,192],"results.":[174,193],"Furthermore,":[175],"comparison":[177],"between":[178],"shows":[181,201],"six":[186],"gives,":[188],"average,":[190],"Finally,":[194],"also":[196],"perform":[197],"frequency-price":[198,209],"analysis":[199],"which":[200],"better":[208],"tradeoff":[210],"compared":[212],"other":[214],"consideration.":[218]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}