{"id":"https://openalex.org/W2555186802","doi":"https://doi.org/10.1145/2987386.2987395","title":"Collaboration of Merge Operations in Hybrid-Mapped Flash Translation Layers with the Multi-Controller Design","display_name":"Collaboration of Merge Operations in Hybrid-Mapped Flash Translation Layers with the Multi-Controller Design","publication_year":2016,"publication_date":"2016-10-11","ids":{"openalex":"https://openalex.org/W2555186802","doi":"https://doi.org/10.1145/2987386.2987395","mag":"2555186802"},"language":"en","primary_location":{"id":"doi:10.1145/2987386.2987395","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2987386.2987395","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Research in Adaptive and Convergent Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023777698","display_name":"Hung-Yi Sung","orcid":null},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hung-Yi Sung","raw_affiliation_strings":["Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101718729","display_name":"Chin-Hsien Wu","orcid":"https://orcid.org/0000-0002-8704-1483"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chin-Hsien Wu","raw_affiliation_strings":["Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032407977","display_name":"Dereje Tekilu","orcid":"https://orcid.org/0000-0003-0421-1051"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Dereje Tekilu","raw_affiliation_strings":["Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5023777698"],"corresponding_institution_ids":["https://openalex.org/I154864474"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15080123,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"181","last_page":"186"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9162999987602234,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.844431459903717},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.785294234752655},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7712893486022949},{"id":"https://openalex.org/keywords/flash-file-system","display_name":"Flash file system","score":0.5884252190589905},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46366220712661743},{"id":"https://openalex.org/keywords/solid-state","display_name":"Solid-state","score":0.41910433769226074},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31662383675575256},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2751811146736145},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20262372493743896},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10294294357299805},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08605238795280457},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.0854177474975586}],"concepts":[{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.844431459903717},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.785294234752655},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7712893486022949},{"id":"https://openalex.org/C27670709","wikidata":"https://www.wikidata.org/wiki/Q5457555","display_name":"Flash file system","level":4,"score":0.5884252190589905},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46366220712661743},{"id":"https://openalex.org/C107814960","wikidata":"https://www.wikidata.org/wiki/Q611957","display_name":"Solid-state","level":2,"score":0.41910433769226074},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31662383675575256},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2751811146736145},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20262372493743896},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10294294357299805},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08605238795280457},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.0854177474975586},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2987386.2987395","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2987386.2987395","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Research in Adaptive and Convergent Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W628515903","https://openalex.org/W2001362066","https://openalex.org/W2010263580","https://openalex.org/W2018763861","https://openalex.org/W2061863403","https://openalex.org/W2106117073","https://openalex.org/W2109966220","https://openalex.org/W2110395205","https://openalex.org/W2114828666","https://openalex.org/W2150230714","https://openalex.org/W2151303863","https://openalex.org/W2164623468","https://openalex.org/W2506188977"],"related_works":["https://openalex.org/W2351735955","https://openalex.org/W2368755666","https://openalex.org/W1994627759","https://openalex.org/W628515903","https://openalex.org/W2393457990","https://openalex.org/W1985253609","https://openalex.org/W2007870656","https://openalex.org/W2151938765","https://openalex.org/W2351380390","https://openalex.org/W2350469736"],"abstract_inverted_index":{"Nowadays,":[0],"the":[1,28,36,41,70,75,78,85,90,91],"architecture":[2],"of":[3,31,38,44,61,94],"solid-state":[4],"drives":[5],"(SSDs)":[6],"is":[7],"using":[8],"multiple":[9],"controllers":[10],"to":[11,26,74,98],"efficiently":[12],"handle":[13],"NAND":[14,32],"ash":[15,19,33,66,79],"memory":[16],"chips.":[17],"Several":[18],"translation":[20,67,80],"layers":[21,68],"(FTLs)":[22],"have":[23],"been":[24],"proposed":[25,86],"improve":[27],"overall":[29],"performance":[30],"memory.":[34],"Therefore,":[35],"collaboration":[37,59],"FTLs":[39],"and":[40],"multi-controller":[42,71],"design":[43],"SSDs":[45],"will":[46,56],"become":[47],"an":[48],"important":[49],"research":[50],"topic.":[51],"In":[52],"this":[53],"paper,":[54],"we":[55],"propose":[57],"a":[58],"method":[60,87],"merge":[62,95],"operations":[63,96],"in":[64],"hybrid-mapped":[65],"with":[69,84],"design.":[72],"According":[73],"experimental":[76],"results,":[77],"layer":[81],"(i.e.,":[82],"FAST)":[83],"can":[88],"reduce":[89],"execution":[92],"time":[93],"up":[97],"16.08%.":[99]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
