{"id":"https://openalex.org/W2559901034","doi":"https://doi.org/10.1145/2974022","title":"Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System","display_name":"Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System","publication_year":2016,"publication_date":"2016-12-09","ids":{"openalex":"https://openalex.org/W2559901034","doi":"https://doi.org/10.1145/2974022","mag":"2559901034"},"language":"en","primary_location":{"id":"doi:10.1145/2974022","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2974022","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000808423","display_name":"Henry Wong","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Henry Wong","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090184149","display_name":"Jonathan Rose","orcid":"https://orcid.org/0000-0002-3551-2175"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jonathan Rose","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada"],"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5000808423"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.6307,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.69136731,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"10","issue":"1","first_page":"1","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8500293493270874},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.7110060453414917},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6041824817657471},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4964213967323303},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4605620801448822},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4468044340610504},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.44536250829696655},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43673044443130493},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.4164939224720001},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.40961605310440063},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32098862528800964},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.19402188062667847}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8500293493270874},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.7110060453414917},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6041824817657471},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4964213967323303},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4605620801448822},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4468044340610504},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.44536250829696655},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43673044443130493},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.4164939224720001},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.40961605310440063},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32098862528800964},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.19402188062667847}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2974022","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2974022","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1562605315","https://openalex.org/W1686420892","https://openalex.org/W1994089185","https://openalex.org/W2016889342","https://openalex.org/W2022807575","https://openalex.org/W2030959856","https://openalex.org/W2062430565","https://openalex.org/W2078726412","https://openalex.org/W2119786518","https://openalex.org/W2135300877","https://openalex.org/W2163099178","https://openalex.org/W2163820265","https://openalex.org/W2484072889","https://openalex.org/W2588464298","https://openalex.org/W2795956964","https://openalex.org/W4243872270","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2132842408","https://openalex.org/W1934130410","https://openalex.org/W2765996788","https://openalex.org/W2109715593","https://openalex.org/W2112915496","https://openalex.org/W2954442117","https://openalex.org/W2051777799","https://openalex.org/W2404820046","https://openalex.org/W2078054742","https://openalex.org/W2168202209"],"abstract_inverted_index":{"Although":[0],"FPGAs":[1],"have":[2,9],"grown":[3,10],"in":[4,21,61],"capacity,":[5],"FPGA-based":[6],"soft":[7],"processors":[8,27],"very":[11],"little":[12],"because":[13],"of":[14,17,40,64,79,94],"the":[15,33,62,71,92,125],"difficulty":[16],"achieving":[18],"higher":[19],"performance":[20,30],"exchange":[22],"for":[23,75,91],"area.":[24],"Superscalar":[25],"out-of-order":[26,80],"promise":[28],"large":[29],"gains,":[31],"and":[32,55,58,83,90,105,116],"memory":[34,67,81,84,129],"subsystem":[35],"is":[36],"a":[37,42,66,95,111],"key":[38],"part":[39],"such":[41,65],"processor":[43],"that":[44],"must":[45],"help":[46],"supply":[47],"increased":[48],"performance.":[49],"In":[50],"this":[51],"article,":[52],"we":[53,108],"describe":[54],"explore":[56],"microarchitectural":[57],"circuit-level":[59],"tradeoffs":[60],"design":[63],"system.":[68,130],"We":[69],"show":[70],"significant":[72],"instructions-per-cycle":[73],"wins":[74],"providing":[76],"various":[77],"levels":[78],"access":[82],"dependence":[85],"speculation":[86],"(1.32":[87],"\u00d7":[88,100],"SPECint2000)":[89],"addition":[93],"second-level":[96],"cache":[97,117],"(another":[98],"1.60":[99],").":[101],"With":[102],"careful":[103],"microarchitecture":[104],"circuit":[106],"design,":[107],"also":[109],"achieve":[110],"L1":[112],"translation":[113],"lookaside":[114],"buffers":[115],"lookup":[118],"with":[119],"29%":[120],"less":[121],"logic":[122],"delay":[123],"than":[124],"simpler":[126],"Nios":[127],"II/f":[128]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
