{"id":"https://openalex.org/W2538165366","doi":"https://doi.org/10.1145/2966986.2980083","title":"UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing","display_name":"UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing","publication_year":2016,"publication_date":"2016-10-18","ids":{"openalex":"https://openalex.org/W2538165366","doi":"https://doi.org/10.1145/2966986.2980083","mag":"2538165366"},"language":"en","primary_location":{"id":"doi:10.1145/2966986.2980083","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2980083","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034982668","display_name":"Wuxi Li","orcid":"https://orcid.org/0000-0002-9887-5109"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wuxi Li","raw_affiliation_strings":["University of Texas at Austin"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015818630","display_name":"Shounak Dhar","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shounak Dhar","raw_affiliation_strings":["University of Texas at Austin"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["University of Texas at Austin"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5034982668"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":2.7565,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.91109462,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8113679885864258},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6650095582008362},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5154791474342346},{"id":"https://openalex.org/keywords/contest","display_name":"CONTEST","score":0.5130959749221802},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.48398566246032715},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.43330106139183044},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4330781400203705},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.14732307195663452}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8113679885864258},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6650095582008362},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5154791474342346},{"id":"https://openalex.org/C2777582232","wikidata":"https://www.wikidata.org/wiki/Q5013414","display_name":"CONTEST","level":2,"score":0.5130959749221802},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.48398566246032715},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.43330106139183044},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4330781400203705},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.14732307195663452},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2966986.2980083","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2980083","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1583136220","https://openalex.org/W1963908543","https://openalex.org/W1978383095","https://openalex.org/W1986026297","https://openalex.org/W2002641171","https://openalex.org/W2020549672","https://openalex.org/W2021149030","https://openalex.org/W2029031086","https://openalex.org/W2055251702","https://openalex.org/W2057469119","https://openalex.org/W2075137913","https://openalex.org/W2106448546","https://openalex.org/W2111756578","https://openalex.org/W2113267287","https://openalex.org/W2119354760","https://openalex.org/W2124537194","https://openalex.org/W2135606070","https://openalex.org/W2137454730","https://openalex.org/W2138206217","https://openalex.org/W2139637699","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2154014710","https://openalex.org/W2154302973","https://openalex.org/W2158961316","https://openalex.org/W2162141797","https://openalex.org/W2165419774","https://openalex.org/W2167190617","https://openalex.org/W2168048050","https://openalex.org/W2328615082","https://openalex.org/W6680484343"],"related_works":["https://openalex.org/W3183044703","https://openalex.org/W2082487009","https://openalex.org/W2132668926","https://openalex.org/W2156550631","https://openalex.org/W2042759115","https://openalex.org/W1973505932","https://openalex.org/W2547355295","https://openalex.org/W2914442136","https://openalex.org/W2098851424","https://openalex.org/W2159053194"],"abstract_inverted_index":{"FPGA":[0,16,37,75],"packing":[1,17,38,56],"and":[2,18,39,48,53,58,83],"placement":[3,19,40,63,76],"without":[4],"routability":[5],"consideration":[6],"could":[7],"lead":[8],"to":[9,23,27],"unroutable":[10],"results":[11],"for":[12],"high-utilization":[13],"designs.":[14],"Conventional":[15],"approaches":[20],"are":[21,65],"shown":[22],"have":[24],"severe":[25],"difficulties":[26],"yield":[28],"good":[29],"routability.":[30],"In":[31],"this":[32],"paper,":[33],"we":[34],"propose":[35],"a":[36],"engine":[41],"called":[42],"UTPlaceF":[43,78],"that":[44],"simultaneously":[45],"optimizes":[46],"wirelength":[47,87],"routablity.":[49],"A":[50],"novel":[51],"physical":[52],"congestion":[54,60],"aware":[55,61],"alogrithm":[57],"several":[59],"detailed":[62],"techniques":[64],"proposed.":[66],"Compared":[67],"with":[68,88],"the":[69],"top":[70],"3":[71],"winners":[72],"of":[73],"ISPD'16":[74],"contest,":[77],"can":[79],"achieve":[80],"3.3%,":[81],"7.7%":[82],"28.3%":[84],"better":[85],"routed":[86],"similar":[89],"or":[90],"shorter":[91],"runtime.":[92]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":10}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}