{"id":"https://openalex.org/W2532108215","doi":"https://doi.org/10.1145/2966986.2980082","title":"Performance driven routing for modern FPGAs","display_name":"Performance driven routing for modern FPGAs","publication_year":2016,"publication_date":"2016-10-18","ids":{"openalex":"https://openalex.org/W2532108215","doi":"https://doi.org/10.1145/2966986.2980082","mag":"2532108215"},"language":"en","primary_location":{"id":"doi:10.1145/2966986.2980082","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2980082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112222457","display_name":"Parivallal Kannan","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Parivallal Kannan","raw_affiliation_strings":["Xilinx Inc","Xilinx Inc., 2100 Logic Dr., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx Inc., 2100 Logic Dr., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025849840","display_name":"Satish Sivaswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Sivaswamy","raw_affiliation_strings":["Xilinx Inc","Xilinx Inc., 2100 Logic Dr., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx Inc., 2100 Logic Dr., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112222457"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.10515056,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6846413612365723},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6373929977416992},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5827714204788208},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48725929856300354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3359116315841675}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6846413612365723},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6373929977416992},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5827714204788208},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48725929856300354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3359116315841675}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2966986.2980082","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2980082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1921869937","https://openalex.org/W1969483458","https://openalex.org/W2011778848","https://openalex.org/W2046662879","https://openalex.org/W2066930380","https://openalex.org/W2100322482","https://openalex.org/W2107375256","https://openalex.org/W2114532661","https://openalex.org/W2166378964","https://openalex.org/W2275304190","https://openalex.org/W2523938169","https://openalex.org/W2752885492","https://openalex.org/W3145128584","https://openalex.org/W3145853217","https://openalex.org/W4206262605"],"related_works":["https://openalex.org/W2002703587","https://openalex.org/W3217667592","https://openalex.org/W71953811","https://openalex.org/W2974799146","https://openalex.org/W2895183628","https://openalex.org/W2140555705","https://openalex.org/W2538691665","https://openalex.org/W2145701142","https://openalex.org/W1986643545","https://openalex.org/W2110373273"],"abstract_inverted_index":{"FPGA":[0,13,167],"routing":[1,9,51],"is":[2],"a":[3,57,71,128],"well":[4,20],"studied":[5],"problem.":[6],"Basic":[7],"point-to-point":[8],"of":[10,49,70,131,171,179],"nets":[11],"on":[12,85],"fabrics":[14],"can":[15],"be":[16],"done":[17],"optimally":[18],"using":[19],"known":[21],"shortest":[22],"path":[23],"algorithms":[24,33],"like":[25,34,106],"Dijkstra's":[26],"and":[27,31,43,74,124,147,157],"A-star.":[28],"Practical":[29],"rip-up":[30],"reroute":[32],"PathFinder":[35],"have":[36,111],"been":[37],"very":[38],"influential":[39],"in":[40],"various":[41,162],"academic":[42],"industrial":[44,93,166],"routers.":[45],"The":[46,134],"relaxed":[47],"version":[48],"the":[50,66,75,79,86,99,107,116,140,172,184],"problem,":[52],"that":[53],"ignores":[54],"congestion,":[55],"has":[56],"polynomial":[58],"time-complexity.":[59],"This":[60],"allows":[61],"us":[62],"to":[63,82,95,115,119,126,142,153,175],"easily":[64],"determine":[65],"best-case":[67,186],"timing":[68,102,177],"performance":[69,178],"placed":[72,180],"design":[73],"degradation":[76],"introduced":[77,112],"by":[78,164],"router":[80,94,141],"due":[81],"congestion":[83,156],"alleviation":[84],"datapath.":[87],"Is":[88],"it":[89],"possible":[90],"for":[91],"an":[92],"actually":[96],"improve":[97,121,176],"upon":[98],"best":[100],"case":[101],"performance?":[103],"Modern":[104],"FPGAs":[105],"Xilinx":[108],"Ultrascale+":[109],"family,":[110],"major":[113],"changes":[114],"clocking":[117,136,173],"architecture":[118],"help":[120],"clock":[122],"skews":[123],"also":[125,138],"support":[127],"large":[129],"number":[130],"user":[132],"clocks.":[133],"new":[135],"architectures":[137],"allow":[139],"perform":[143],"low-cost":[144],"time-borrow":[145],"optimization":[146],"efficient":[148],"high":[149],"fanout":[150],"net":[151],"routing,":[152],"alleviate":[154],"fabric":[155],"simplify":[158],"timing-closure.":[159],"We":[160],"describe":[161],"methods":[163],"which":[165],"routers":[168],"take":[169],"advantage":[170],"features":[174],"circuit":[181],"designs":[182],"beyond":[183],"traditional":[185],"scenarios.":[187]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}