{"id":"https://openalex.org/W2532205282","doi":"https://doi.org/10.1145/2966986.2967080","title":"Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs","display_name":"Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs","publication_year":2016,"publication_date":"2016-10-18","ids":{"openalex":"https://openalex.org/W2532205282","doi":"https://doi.org/10.1145/2966986.2967080","mag":"2532205282"},"language":"en","primary_location":{"id":"doi:10.1145/2966986.2967080","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2967080","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066713236","display_name":"Sandeep Kumar Samal","orcid":"https://orcid.org/0000-0002-2636-9928"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sandeep Kumar Samal","raw_affiliation_strings":["Georgia Institute of Technology","School of ECE, Georgia Institute of Technology, Atlanta, United States"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, United States","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053014378","display_name":"Deepak Kumar Nayak","orcid":"https://orcid.org/0000-0001-9179-4501"},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deepak Nayak","raw_affiliation_strings":["Technology Research, GLOBALFOUNDRIES","Technology Research, GLOBALFOUNDRIES, Santa Clara, CA, United States"],"affiliations":[{"raw_affiliation_string":"Technology Research, GLOBALFOUNDRIES","institution_ids":["https://openalex.org/I35662394"]},{"raw_affiliation_string":"Technology Research, GLOBALFOUNDRIES, Santa Clara, CA, United States","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040351837","display_name":"Motoi Ichihashi","orcid":null},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Motoi Ichihashi","raw_affiliation_strings":["Technology Research, GLOBALFOUNDRIES","Technology Research, GLOBALFOUNDRIES, Santa Clara, CA, United States"],"affiliations":[{"raw_affiliation_string":"Technology Research, GLOBALFOUNDRIES","institution_ids":["https://openalex.org/I35662394"]},{"raw_affiliation_string":"Technology Research, GLOBALFOUNDRIES, Santa Clara, CA, United States","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031558856","display_name":"Srinivasa Banna","orcid":null},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srinivasa Banna","raw_affiliation_strings":["Technology Research, GLOBALFOUNDRIES","Technology Research, GLOBALFOUNDRIES, Santa Clara, CA, United States"],"affiliations":[{"raw_affiliation_string":"Technology Research, GLOBALFOUNDRIES","institution_ids":["https://openalex.org/I35662394"]},{"raw_affiliation_string":"Technology Research, GLOBALFOUNDRIES, Santa Clara, CA, United States","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["Georgia Institute of Technology","School of ECE, Georgia Institute of Technology, Atlanta, United States"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, United States","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5066713236"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":1.8401,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.86916788,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6647985577583313},{"id":"https://openalex.org/keywords/back-end-of-line","display_name":"Back end of line","score":0.6158994436264038},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5668843984603882},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5502195954322815},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.524726927280426},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.522024929523468},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48480406403541565},{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.42963850498199463},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4152160584926605},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3422938883304596},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.25429460406303406},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19653496146202087},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.15486887097358704},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06805792450904846}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6647985577583313},{"id":"https://openalex.org/C2776628375","wikidata":"https://www.wikidata.org/wiki/Q4839229","display_name":"Back end of line","level":3,"score":0.6158994436264038},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5668843984603882},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5502195954322815},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.524726927280426},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.522024929523468},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48480406403541565},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.42963850498199463},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4152160584926605},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3422938883304596},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.25429460406303406},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19653496146202087},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.15486887097358704},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06805792450904846},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2966986.2967080","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2967080","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1964678809","https://openalex.org/W2002806561","https://openalex.org/W2012837493","https://openalex.org/W2013397418","https://openalex.org/W2015952501","https://openalex.org/W2028476288","https://openalex.org/W2095117703","https://openalex.org/W2137483718","https://openalex.org/W2245094412","https://openalex.org/W4232424867","https://openalex.org/W4236269389"],"related_works":["https://openalex.org/W1969790797","https://openalex.org/W3127495135","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W1604746479","https://openalex.org/W1571415011","https://openalex.org/W2541572734","https://openalex.org/W2136403807","https://openalex.org/W4386763835","https://openalex.org/W2142764951"],"abstract_inverted_index":{"In":[0,61,180],"this":[1],"paper,":[2],"we":[3,24,81,163,182],"develop":[4,82],"tier":[5],"partitioning":[6,84,118,178],"strategy":[7],"to":[8,52,70,106,130,168,185,198],"mitigate":[9],"back-end-of-line":[10],"(BEOL)":[11],"interconnect":[12,36,207],"delay":[13,30,111],"degradation":[14,31,112],"and":[15,29,99,113,136,159],"cost":[16,151],"issues":[17],"in":[18,37,76,103,142,146,149,171,189],"monolithic":[19],"3D":[20,71],"ICs":[21],"(M3D).":[22],"First,":[23],"study":[25,43],"the":[26,38,63,77,104,108,121,128,132,138,143,172,190],"routing":[27,68,114,134],"overhead":[28,69],"caused":[32],"by":[33,50],"tungsten":[34,46],"BEOL":[35,47,65,89,150,174],"bottom-tier":[39,59,64,173,191],"of":[40,58,110,166,192],"M3D.":[41],"Our":[42,92,116],"shows":[44],"that":[45],"reduces":[48],"performance":[49],"up":[51,167,184,197],"30%":[53],"at":[54],"4&#x00D7;":[55,169],"resistance":[56,175],"increase":[57,170],"interconnect.":[60],"addition,":[62,181],"adds":[66],"a":[67,154],"nets,":[72],"which":[73],"is":[74],"neglected":[75],"state-of-the-art":[78],"flow.":[79],"Next,":[80],"two":[83],"methods":[85],"targeted":[86],"specifically":[87],"towards":[88],"impact":[90,109],"reduction.":[91],"path-based":[93],"approach":[94],"identifies":[95],"critical":[96],"timing":[97],"paths":[98],"places":[100],"their":[101],"cells":[102],"top-tier":[105,129],"reduce":[107,131],"overhead.":[115],"net-based":[117],"methodology":[119],"confines":[120],"nets":[122],"with":[123,196],"long":[124],"2D":[125,203],"wirelength":[126],"into":[127],"overall":[133],"demand,":[135],"hence":[137],"metal":[139,187],"layer":[140],"usage":[141],"bottom-tier.":[144],"This":[145],"turn":[147],"results":[148],"savings.":[152],"Using":[153],"foundry":[155],"22nm":[156],"FDSOI":[157],"technology":[158],"full-chip":[160],"GDS":[161],"designs,":[162],"achieve":[164],"tolerance":[165],"using":[176],"our":[177,193],"strategy.":[179],"save":[183],"3":[186],"layers":[188],"M3D":[194],"designs":[195],"32%":[199],"power":[200],"savings":[201],"over":[202],"IC":[204],"for":[205],"an":[206],"dominated":[208],"benchmark.":[209]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1}],"updated_date":"2026-03-01T08:55:55.761014","created_date":"2025-10-10T00:00:00"}
