{"id":"https://openalex.org/W2535234615","doi":"https://doi.org/10.1145/2966986.2967055","title":"MrDP","display_name":"MrDP","publication_year":2016,"publication_date":"2016-10-18","ids":{"openalex":"https://openalex.org/W2535234615","doi":"https://doi.org/10.1145/2966986.2967055","mag":"2535234615"},"language":"en","primary_location":{"id":"doi:10.1145/2966986.2967055","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2967055","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000933188","display_name":"Yibo Lin","orcid":"https://orcid.org/0000-0002-0977-2774"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yibo Lin","raw_affiliation_strings":["University of Texas at Austin","ECE Department, University of Texas at Austin, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"ECE Department, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051340429","display_name":"Bei Yu","orcid":"https://orcid.org/0000-0001-6406-4810"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bei Yu","raw_affiliation_strings":["The Chinese University of Hong Kong, NT, Hong Kong","CSE Department, The Chinese University of Hong Kong, NT, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, NT, Hong Kong","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"CSE Department, The Chinese University of Hong Kong, NT, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078415010","display_name":"Xiaoqing Xu","orcid":"https://orcid.org/0000-0002-5314-7669"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaoqing Xu","raw_affiliation_strings":["University of Texas at Austin","ECE Department, University of Texas at Austin, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"ECE Department, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044285298","display_name":"Jhih-Rong Gao","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jhih-Rong Gao","raw_affiliation_strings":["Cadence Design Systems Inc","Cadence Design Systems Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089395977","display_name":"V. Natarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Natarajan Viswanathan","raw_affiliation_strings":["Cadence Design Systems Inc","Cadence Design Systems Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100429106","display_name":"Wenhao Liu","orcid":"https://orcid.org/0000-0001-9757-1077"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wen-Hao Liu","raw_affiliation_strings":["Cadence Design Systems Inc","Cadence Design Systems Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100448026","display_name":"Zhuo Li","orcid":"https://orcid.org/0000-0002-5535-5920"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhuo Li","raw_affiliation_strings":["Cadence Design Systems Inc","Cadence Design Systems Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113656006","display_name":"Charles J. Alpert","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles J. Alpert","raw_affiliation_strings":["Cadence Design Systems Inc","Cadence Design Systems Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems Inc","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["University of Texas at Austin","ECE Department, University of Texas at Austin, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"ECE Department, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5000933188"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":4.0428,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.94252973,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7338571548461914},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6774907112121582},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.633635401725769},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.629447877407074},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5697523355484009},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5072102546691895},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4913271963596344},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4759797155857086},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4696817994117737},{"id":"https://openalex.org/keywords/smoothing","display_name":"Smoothing","score":0.45161229372024536},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4170971214771271},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38327085971832275},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.29970353841781616},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2726741433143616},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2549036145210266}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7338571548461914},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6774907112121582},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.633635401725769},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.629447877407074},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5697523355484009},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5072102546691895},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4913271963596344},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4759797155857086},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4696817994117737},{"id":"https://openalex.org/C3770464","wikidata":"https://www.wikidata.org/wiki/Q775963","display_name":"Smoothing","level":2,"score":0.45161229372024536},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4170971214771271},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38327085971832275},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29970353841781616},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2726741433143616},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2549036145210266},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2966986.2967055","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2966986.2967055","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 35th International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1967661769","https://openalex.org/W1978383095","https://openalex.org/W1986026297","https://openalex.org/W1990485341","https://openalex.org/W1995233983","https://openalex.org/W2003145440","https://openalex.org/W2010747748","https://openalex.org/W2013433346","https://openalex.org/W2014631148","https://openalex.org/W2016074831","https://openalex.org/W2018183393","https://openalex.org/W2034194269","https://openalex.org/W2039556638","https://openalex.org/W2051728103","https://openalex.org/W2054507614","https://openalex.org/W2070853264","https://openalex.org/W2075321943","https://openalex.org/W2081206460","https://openalex.org/W2081873260","https://openalex.org/W2095117703","https://openalex.org/W2110436374","https://openalex.org/W2114136290","https://openalex.org/W2116319078","https://openalex.org/W2129115040","https://openalex.org/W2132693178","https://openalex.org/W2153101534","https://openalex.org/W2161455936","https://openalex.org/W2169862988","https://openalex.org/W2172061077","https://openalex.org/W2293667481","https://openalex.org/W2342916071","https://openalex.org/W2407716185"],"related_works":["https://openalex.org/W2024392966","https://openalex.org/W2167755864","https://openalex.org/W1965232212","https://openalex.org/W2151657833","https://openalex.org/W2070693700","https://openalex.org/W4312327624","https://openalex.org/W4244696039","https://openalex.org/W3021210272","https://openalex.org/W4249416173","https://openalex.org/W4245549415"],"abstract_inverted_index":{"As":[0],"VLSI":[1],"technology":[2],"shrinks":[3],"to":[4,13,51,69,84,146],"fewer":[5],"tracks":[6],"per":[7],"standard":[8,133],"cell,":[9],"e.g.,":[10],"from":[11],"10-track":[12],"7.5-track":[14],"libraries":[15],"(and":[16],"lesser":[17],"for":[18,39,110,174,201,227],"7nm),":[19],"there":[20],"has":[21],"been":[22],"a":[23,71,107,169,181,195],"rapid":[24],"increase":[25],"in":[26,214],"the":[27,43,80,129,187,209,222],"usage":[28,44],"of":[29,45,101,103,119,131,141,180,189,211],"multiple-row":[30,104,121],"cells":[31,56,122,134,191],"like":[32],"two-":[33],"and":[34,92,126,156,203,217],"three-row":[35],"flip-flops,":[36],"buffers,":[37],"etc.,":[38],"design":[40,61,81,86,113],"closure.":[41],"Additionally,":[42],"multi-bit":[46],"flip-flops":[47],"or":[48],"flop":[49],"trays":[50],"save":[52],"power":[53],"creates":[54],"large":[55],"that":[57,150,185],"further":[58],"complicate":[59],"critical":[60,112],"tasks,":[62],"such":[63,88],"as":[64,192,194],"placement.":[65,163],"Detailed":[66],"placement":[67,125],"happens":[68],"be":[70],"key":[72],"optimization":[73],"transform,":[74],"which":[75],"is":[76,144],"repeatedly":[77],"invoked":[78],"during":[79,123,161],"closure":[82,114],"flow":[83],"improve":[85],"parameters,":[87],"as,":[89],"wirelength,":[90],"timing,":[91],"local":[93],"wiring":[94],"congestion.":[95],"Advanced":[96],"node":[97],"designs,":[98],"with":[99,221,229],"hundreds":[100],"thousands":[102],"cells,":[105],"require":[106],"paradigm":[108],"change":[109],"this":[111,165],"transform.":[115],"The":[116],"traditional":[117],"approach":[118,178,200],"fixing":[120],"detailed":[124,162,172,225],"only":[127],"optimizing":[128],"locations":[130,160],"single-row":[132,157],"can":[135,151],"no":[136],"longer":[137],"obtain":[138],"appreciable":[139],"quality":[140],"results.":[142],"It":[143],"imperative":[145],"have":[147],"new":[148,170],"techniques":[149,213],"simultaneously":[152],"optimize":[153],"both":[154],"multiple-":[155],"high":[158],"cell":[159],"In":[164],"paper,":[166],"we":[167],"propose":[168],"density-aware":[171],"placer":[173,226],"heterogeneous-sized":[175,190,230],"netlists.":[176],"Our":[177],"consists":[179],"chain":[182],"move":[183],"scheme":[184],"generalizes":[186],"movement":[188],"well":[193],"nested":[196],"dynamic":[197],"programming":[198],"based":[199],"wirelength":[202,215],"density":[204,218],"optimization.":[205],"Experimental":[206],"results":[207],"demonstrate":[208],"effectiveness":[210],"these":[212],"minimization":[216],"smoothing":[219],"compared":[220],"most":[223],"recent":[224],"designs":[228],"cells.":[231]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":10}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-10-28T00:00:00"}