{"id":"https://openalex.org/W2501612408","doi":"https://doi.org/10.1145/2934583.2953983","title":"Dissecting Xeon + FPGA","display_name":"Dissecting Xeon + FPGA","publication_year":2016,"publication_date":"2016-07-29","ids":{"openalex":"https://openalex.org/W2501612408","doi":"https://doi.org/10.1145/2934583.2953983","mag":"2501612408"},"language":"en","primary_location":{"id":"doi:10.1145/2934583.2953983","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2934583.2953983","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078387900","display_name":"Herman Schmit","orcid":"https://orcid.org/0000-0002-0109-7604"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Herman Schmit","raw_affiliation_strings":["Intel Corporation, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074836221","display_name":"Randy Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Randy Huang","raw_affiliation_strings":["Intel Corporation, San Jose, CA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5078387900"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.02472646,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.88165629,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"152","last_page":"153"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7877410054206848},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7581806182861328},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7228882312774658},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.6523259878158569},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47211754322052},{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.4597629904747009},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4385153651237488},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.43496400117874146},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42038604617118835},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25837773084640503}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7877410054206848},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7581806182861328},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7228882312774658},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.6523259878158569},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47211754322052},{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.4597629904747009},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4385153651237488},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.43496400117874146},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42038604617118835},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25837773084640503}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2934583.2953983","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2934583.2953983","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2115294662","https://openalex.org/W2163605009","https://openalex.org/W2300242332","https://openalex.org/W2469490737","https://openalex.org/W2618530766","https://openalex.org/W3147600416"],"related_works":["https://openalex.org/W2993910401","https://openalex.org/W1974923383","https://openalex.org/W2475524688","https://openalex.org/W2739740241","https://openalex.org/W2085105049","https://openalex.org/W2526069705","https://openalex.org/W2024016913","https://openalex.org/W2019153376","https://openalex.org/W2981664121","https://openalex.org/W2796552083"],"abstract_inverted_index":{"Intel's":[0],"Xeon":[1],"roadmap":[2],"includes":[3],"package-integrated":[4],"FPGAs":[5,78],"in":[6,29,49],"every":[7],"new":[8],"generation.":[9],"In":[10],"this":[11,17,24,84],"talk,":[12],"we":[13,62,88],"will":[14,33,63,89],"dissect":[15],"why":[16],"is":[18,42,113],"such":[19],"a":[20,43,53],"powerful":[21],"combination":[22],"at":[23],"time":[25],"of":[26,59,68,93,97,121],"great":[27],"change":[28],"datacenter":[30,51],"workloads.":[31],"We":[32],"show":[34],"how":[35],"power":[36,47],"savings":[37,48],"within":[38],"the":[39,50,57,65,75,80,91,94,98,101,116],"CPU":[40,99],"complex":[41],"significant":[44],"multiplier":[45],"for":[46,115],"as":[52],"whole.":[54],"Focusing":[55],"on":[56],"domain":[58],"machine":[60],"learning,":[61],"present":[64],"recent":[66],"evolution":[67],"data":[69],"types":[70],"and":[71,73,100,108,119],"operators,":[72],"make":[74],"case":[76],"that":[77,112],"are":[79],"path":[81],"to":[82],"facilitate":[83],"continued":[85],"evolution.":[86],"Finally,":[87],"discuss":[90],"criticality":[92],"close":[95],"coupling":[96,104],"FPGA.":[102],"This":[103],"facilitates":[105],"high":[106],"bandwidth":[107],"low":[109],"latency":[110],"communication":[111],"required":[114],"development,":[117],"debugging":[118],"deployment":[120],"heterogeneous":[122],"applications.":[123]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
