{"id":"https://openalex.org/W2345147456","doi":"https://doi.org/10.1145/2927964.2927970","title":"Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq","display_name":"Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq","publication_year":2016,"publication_date":"2016-04-22","ids":{"openalex":"https://openalex.org/W2345147456","doi":"https://doi.org/10.1145/2927964.2927970","mag":"2345147456"},"language":"en","primary_location":{"id":"doi:10.1145/2927964.2927970","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2927964.2927970","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076243389","display_name":"Abhishek Kumar Jain","orcid":"https://orcid.org/0000-0003-3797-029X"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Abhishek Kumar Jain","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083911874","display_name":"Xiangwei Li","orcid":"https://orcid.org/0000-0002-1963-6354"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Xiangwei Li","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032556461","display_name":"Suhaib A. Fahmy","orcid":"https://orcid.org/0000-0003-0568-5048"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Suhaib A. Fahmy","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059218594","display_name":"Douglas L. Maskell","orcid":"https://orcid.org/0000-0002-6588-4762"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Douglas L. Maskell","raw_affiliation_strings":["Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5076243389"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":5.7978,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.96466269,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"43","issue":"4","first_page":"28","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7703949213027954},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6845933794975281},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6279460787773132},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6208598017692566},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5906823873519897},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.5606884360313416},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5384106636047363},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4588319659233093},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4537901282310486},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18980661034584045}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7703949213027954},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6845933794975281},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6279460787773132},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6208598017692566},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5906823873519897},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.5606884360313416},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5384106636047363},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4588319659233093},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4537901282310486},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18980661034584045},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2927964.2927970","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2927964.2927970","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1969529818","https://openalex.org/W1969816685","https://openalex.org/W1970047515","https://openalex.org/W1971086750","https://openalex.org/W1986687470","https://openalex.org/W1992336996","https://openalex.org/W2017517691","https://openalex.org/W2022497217","https://openalex.org/W2051119615","https://openalex.org/W2052930524","https://openalex.org/W2064514610","https://openalex.org/W2080556528","https://openalex.org/W2105311743","https://openalex.org/W2107350738","https://openalex.org/W2130408605","https://openalex.org/W2141418654","https://openalex.org/W2142501475","https://openalex.org/W2147345262","https://openalex.org/W2158824786","https://openalex.org/W2172212694"],"related_works":["https://openalex.org/W1657880117","https://openalex.org/W2595172197","https://openalex.org/W2127970246","https://openalex.org/W2084856301","https://openalex.org/W1001352512","https://openalex.org/W4382618745","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882"],"abstract_inverted_index":{"Coarse-grained":[0],"overlay":[1,54],"architectures":[2,25],"have":[3],"been":[4],"shown":[5],"to":[6,125],"be":[7],"effective":[8],"when":[9],"paired":[10,60],"with":[11,61],"general":[12,27,63],"purpose":[13,28,64],"processors,":[14],"offering":[15],"software-like":[16],"programmability,":[17],"fast":[18],"compilation,":[19],"and":[20,46,85,94,120],"improved":[21,101],"design":[22,33],"productivity.":[23],"These":[24],"enable":[26],"hardware":[29,32,58],"accelerators,":[30],"allowing":[31],"at":[34,41],"a":[35,57,62,67,91,115],"higher":[36],"level":[37],"of":[38,44,108],"abstraction,":[39],"but":[40],"the":[42,52,72,77,82,106,109,126,138,142],"cost":[43],"area":[45,93,122],"performance":[47,95],"overheads.":[48],"This":[49],"paper":[50],"examines":[51],"DySER":[53,78],"architecture":[55,79,104,140],"as":[56,71],"accelerator":[59],"processor":[65],"in":[66,114,137,144],"hybrid":[68],"FPGA":[69],"such":[70],"Xilinx":[73,83],"Zynq.":[74],"We":[75,97,131],"evaluate":[76],"mapped":[80],"on":[81],"Zynq":[84],"show":[86],"that":[87,133],"it":[88],"suffers":[89],"from":[90],"significant":[92],"overhead.":[96],"then":[98],"propose":[99],"an":[100],"functional":[102,128],"unit":[103,129],"using":[105],"flexibility":[107],"DSP48E1":[110],"primitive":[111],"which":[112],"results":[113,136],"2.5":[116],"times":[117],"frequency":[118],"improvement":[119,135],"25%":[121],"reduction":[123],"compared":[124],"original":[127],"architecture.":[130],"demonstrate":[132],"this":[134],"routing":[139],"becoming":[141],"bottleneck":[143],"performance.":[145]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}