{"id":"https://openalex.org/W2517439447","doi":"https://doi.org/10.1145/2905055.2905321","title":"Low-Power High Speed 1-bit Full Adder Circuit Design","display_name":"Low-Power High Speed 1-bit Full Adder Circuit Design","publication_year":2016,"publication_date":"2016-03-04","ids":{"openalex":"https://openalex.org/W2517439447","doi":"https://doi.org/10.1145/2905055.2905321","mag":"2517439447"},"language":"en","primary_location":{"id":"doi:10.1145/2905055.2905321","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2905055.2905321","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081351572","display_name":"Shailesh K. Dwivedi","orcid":null},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Shailesh Dwivedi","raw_affiliation_strings":["Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083830820","display_name":"Kavita Khare","orcid":"https://orcid.org/0000-0002-7704-7646"},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kavita Khare","raw_affiliation_strings":["Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019230725","display_name":"Ajay Kumar Dadoria","orcid":"https://orcid.org/0000-0002-2947-8257"},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ajay Kumar Dadoria","raw_affiliation_strings":["Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5081351572"],"corresponding_institution_ids":["https://openalex.org/I91277730"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.57782724,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9524469971656799},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.779493510723114},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.7518606781959534},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6711313724517822},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5344390869140625},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5189792513847351},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4563068449497223},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4304279088973999},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3883223831653595},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1860429048538208},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06817474961280823}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9524469971656799},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.779493510723114},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.7518606781959534},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6711313724517822},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5344390869140625},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5189792513847351},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4563068449497223},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4304279088973999},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3883223831653595},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1860429048538208},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06817474961280823}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2905055.2905321","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2905055.2905321","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320318908","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1842156172","https://openalex.org/W1968987637","https://openalex.org/W1993091105","https://openalex.org/W1993454966","https://openalex.org/W1994627436","https://openalex.org/W2007043968","https://openalex.org/W2025315299","https://openalex.org/W2046103068","https://openalex.org/W2076136595","https://openalex.org/W2103490953","https://openalex.org/W2124278579","https://openalex.org/W2138031427","https://openalex.org/W2138968074","https://openalex.org/W2139978032","https://openalex.org/W2141849037","https://openalex.org/W2162211138","https://openalex.org/W4242826795"],"related_works":["https://openalex.org/W2527731084","https://openalex.org/W2619307913","https://openalex.org/W4200113551","https://openalex.org/W2376573441","https://openalex.org/W2187717486","https://openalex.org/W3161678484","https://openalex.org/W4225985484","https://openalex.org/W1863387014","https://openalex.org/W4385009842","https://openalex.org/W3037574826"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"presented":[4],"a":[5,43,51,142],"new":[6,55],"13T":[7],"full":[8],"adder":[9,41],"design":[10,16,56,104],"based":[11],"on":[12,46,84],"hybrid":[13],"--CMOS":[14],"logic":[15],"style.":[17],"Adders":[18],"are":[19,81,95],"one":[20],"of":[21,39,50,101,111],"the":[22,32,47,79,92,99,102,106],"most":[23],"basic":[24],"building":[25],"blocks":[26],"in":[27,31,145,152],"digital":[28,52],"components":[29],"present":[30],"Arithmetic":[33],"Logic":[34],"Unit":[35],"(ALU).":[36],"The":[37,54,137],"performance":[38,49],"an":[40],"have":[42],"significant":[44,129],"impact":[45],"overall":[48],"system.":[53],"is":[57,115,122,131],"compared":[58],"with":[59,124,150],"some":[60],"existing":[61,107],"designs":[62],"for":[63],"power":[64,112,138],"consumption,":[65],"delay,":[66],"PDP":[67],"at":[68,87,116,133,141],"various":[69],"frequencies":[70,135],"viz":[71],"10":[72],"MHz,":[73],"200":[74],"MHz":[75],"and":[76,91,128],"1":[77],"GHz.":[78],"simulations":[80],"carried":[82],"out":[83],"Cadence":[85],"Virtuoso":[86],"180nm":[88],"CMOS":[89],"technology":[90],"simulation":[93],"results":[94],"analyzed":[96],"to":[97,126,147],"verify":[98],"superiority":[100],"proposed":[103,120],"over":[105],"designs.":[108],"Maximum":[109],"saving":[110],"delay":[113],"product":[114],"low":[117],"frequency":[118],"by":[119],"circuit":[121],"96.8%":[123],"respect":[125],"C-CMOS":[127],"improvement":[130],"observed":[132],"other":[134,148],"also.":[136],"consumption":[139],"increases":[140],"slow":[143],"rate":[144],"comparison":[146],"adders":[149],"increase":[151],"frequency.":[153]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
