{"id":"https://openalex.org/W2516243021","doi":"https://doi.org/10.1145/2905055.2905303","title":"Novel Gating Technique in D-Latch for Low Power Application","display_name":"Novel Gating Technique in D-Latch for Low Power Application","publication_year":2016,"publication_date":"2016-03-04","ids":{"openalex":"https://openalex.org/W2516243021","doi":"https://doi.org/10.1145/2905055.2905303","mag":"2516243021"},"language":"en","primary_location":{"id":"doi:10.1145/2905055.2905303","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2905055.2905303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033813467","display_name":"Akanksha Singh","orcid":"https://orcid.org/0000-0002-3823-8140"},"institutions":[{"id":"https://openalex.org/I191366470","display_name":"ITM University","ror":"https://ror.org/004pc5924","country_code":"IN","type":"education","lineage":["https://openalex.org/I191366470"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Akanksha Singh","raw_affiliation_strings":["ECE Department, ITM University, Gwalior, M.P"],"affiliations":[{"raw_affiliation_string":"ECE Department, ITM University, Gwalior, M.P","institution_ids":["https://openalex.org/I191366470"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039097413","display_name":"Ayushi Marwah","orcid":null},"institutions":[{"id":"https://openalex.org/I191366470","display_name":"ITM University","ror":"https://ror.org/004pc5924","country_code":"IN","type":"education","lineage":["https://openalex.org/I191366470"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ayushi Marwah","raw_affiliation_strings":["ECE Department, ITM University, Gwalior, M.P"],"affiliations":[{"raw_affiliation_string":"ECE Department, ITM University, Gwalior, M.P","institution_ids":["https://openalex.org/I191366470"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038669516","display_name":"Shyam Akashe","orcid":"https://orcid.org/0000-0001-6240-1967"},"institutions":[{"id":"https://openalex.org/I191366470","display_name":"ITM University","ror":"https://ror.org/004pc5924","country_code":"IN","type":"education","lineage":["https://openalex.org/I191366470"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shyam Akashe","raw_affiliation_strings":["ECE Department, ITM University, Gwalior, M.P"],"affiliations":[{"raw_affiliation_string":"ECE Department, ITM University, Gwalior, M.P","institution_ids":["https://openalex.org/I191366470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5033813467"],"corresponding_institution_ids":["https://openalex.org/I191366470"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08653999,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.8835034966468811},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.8013948202133179},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.6839668154716492},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.6303956508636475},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5885822772979736},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5341189503669739},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5147390365600586},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5058331489562988},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4923454523086548},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.44688481092453003},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.42838191986083984},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4241184890270233},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.38678720593452454},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37170886993408203},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.31392237544059753},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2349528670310974},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.19913381338119507}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8835034966468811},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.8013948202133179},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.6839668154716492},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.6303956508636475},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5885822772979736},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5341189503669739},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5147390365600586},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5058331489562988},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4923454523086548},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.44688481092453003},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.42838191986083984},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4241184890270233},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.38678720593452454},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37170886993408203},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.31392237544059753},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2349528670310974},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.19913381338119507},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2905055.2905303","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2905055.2905303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1968632892","https://openalex.org/W1994564481","https://openalex.org/W2028332523","https://openalex.org/W2040438223","https://openalex.org/W2045858890","https://openalex.org/W2047207601","https://openalex.org/W2128942741","https://openalex.org/W2172010302","https://openalex.org/W2624408496","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W4386968318","https://openalex.org/W3006003651","https://openalex.org/W2337711143","https://openalex.org/W2137310043","https://openalex.org/W2088914741","https://openalex.org/W2495024767","https://openalex.org/W2040807843","https://openalex.org/W4247180033","https://openalex.org/W2559451387"],"abstract_inverted_index":{"This":[0],"paper":[1],"is":[2,29,59,82,110,115,131],"presented":[3],"with":[4,79],"the":[5,15,27,32,41,54,63,67,71,86,90,94,97,102,104,107,118,134],"comparison":[6],"of":[7,34,48,56,85,106],"gating":[8,21,99],"techniques":[9,22],"which":[10],"are":[11,23],"being":[12,24],"applied":[13,25],"in":[14,26,40,50,70,93,101,117,133,138],"dynamic":[16,72,91],"latch":[17,73],"comparator":[18,74],"circuit.":[19,95],"Clock":[20,44],"circuit":[28,42,103,130],"used":[30],"for":[31],"reduction":[33],"leakage":[35,127],"and":[36],"other":[37],"power":[38,49,92,121],"consumption":[39],"designed.":[43],"consumes":[45],"about":[46],"70%":[47],"any":[51],"circuit,":[52],"so":[53],"controlling":[55,62],"clock":[57,64,87,98,108],"signal":[58,65,88,109],"required.":[60],"By":[61],"using":[66],"desired":[68],"technique":[69,100],"design":[75],"a":[76],"better":[77,113],"output":[78],"higher":[80],"performance":[81,114],"observed.":[83],"Controlling":[84],"reduces":[89],"Using":[96],"switching":[105],"controlled.":[111],"A":[112],"observed":[116],"parameters":[119],"like":[120],"consumption,":[122],"voltage":[123],"gain,":[124],"efficiency,":[125],"delay,":[126],"power.":[128],"The":[129],"simulated":[132],"cadence":[135],"virtuoso":[136],"tool":[137],"45nm":[139],"technology.":[140]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}