{"id":"https://openalex.org/W2353619486","doi":"https://doi.org/10.1145/2902961.2903006","title":"ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System","display_name":"ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System","publication_year":2016,"publication_date":"2016-05-13","ids":{"openalex":"https://openalex.org/W2353619486","doi":"https://doi.org/10.1145/2902961.2903006","mag":"2353619486"},"language":"en","primary_location":{"id":"doi:10.1145/2902961.2903006","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2902961.2903006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2117/98230","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048708476","display_name":"Jordi P\u00e9rez\u2010Puigdemont","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Jordi P\u00e9rez-Puigdemont","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028715959","display_name":"Francesc Moll","orcid":"https://orcid.org/0000-0002-1290-3253"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Francesc Moll","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048708476"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":0.3504,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.63159253,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"381","last_page":"384"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.8498035669326782},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.6433448195457458},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6346087455749512},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.6020510792732239},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5571526885032654},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5488241314888},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.48154643177986145},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47155141830444336},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.44623807072639465},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4181605875492096},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.37370795011520386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3377293646335602},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3144550025463104},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.26367032527923584},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2465524971485138},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.2418186366558075},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20350930094718933},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09907087683677673},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09547537565231323}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8498035669326782},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.6433448195457458},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6346087455749512},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.6020510792732239},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5571526885032654},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5488241314888},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.48154643177986145},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47155141830444336},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.44623807072639465},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4181605875492096},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.37370795011520386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3377293646335602},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3144550025463104},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.26367032527923584},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2465524971485138},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2418186366558075},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20350930094718933},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09907087683677673},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09547537565231323}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2902961.2903006","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2902961.2903006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:upcommons.upc.edu:2117/98230","is_oa":false,"landing_page_url":"https://hdl.handle.net/2117/98230","pdf_url":null,"source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:www.recercat.cat:2072/269944","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/98230","pdf_url":null,"source":{"id":"https://openalex.org/S4306402147","display_name":"RECERCAT (Consorci de Serveis Universitaris de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210090028","host_organization_name":"Consorci de Serveis Universitaris de Catalunya","host_organization_lineage":["https://openalex.org/I4210090028"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"pmh:oai:www.recercat.cat:2072/269944","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/98230","pdf_url":null,"source":{"id":"https://openalex.org/S4306402147","display_name":"RECERCAT (Consorci de Serveis Universitaris de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210090028","host_organization_name":"Consorci de Serveis Universitaris de Catalunya","host_organization_lineage":["https://openalex.org/I4210090028"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"score":0.7799999713897705,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G1059382460","display_name":null,"funder_award_id":"TEC2013-45638-C3-2-R","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"}],"funders":[{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1981384041","https://openalex.org/W2015917466","https://openalex.org/W2020656014","https://openalex.org/W2033443176","https://openalex.org/W2074197361","https://openalex.org/W2092832068","https://openalex.org/W2137891515"],"related_works":["https://openalex.org/W2124909075","https://openalex.org/W2169622190","https://openalex.org/W2224788396","https://openalex.org/W2117541676","https://openalex.org/W1607003253","https://openalex.org/W2169618112","https://openalex.org/W3013924136","https://openalex.org/W2171851068","https://openalex.org/W2496244846","https://openalex.org/W2143420037"],"abstract_inverted_index":{"An":[0],"all-digital":[1],"self-adaptive":[2],"clock":[3,11,43,125],"generation":[4],"system":[5,84,105],"capable":[6],"of":[7,17],"autonomously":[8],"adapt":[9],"the":[10,15,52,61,70,74,104,119,124,128],"frequency":[12,50],"to":[13,51,65,79,102,127],"compensate":[14],"effects":[16],"static":[18],"spatially":[19],"heterogeneous":[20],"(SSHet)":[21],"PVTA":[22,53],"variations":[23,54,68],"is":[24],"presented.":[25],"The":[26,45,82,96],"design":[27],"uses":[28],"time-to-digital":[29],"converters":[30],"(TDCs)":[31],"as":[32,42],"delay":[33],"sensors":[34],"and":[35,72,122],"a":[36,89,93],"variable":[37],"length":[38,76],"ring":[39],"oscillator":[40],"(VLRO)":[41],"generator.":[44],"VLRO":[46,75,120],"naturally":[47],"adapts":[48,118],"its":[49,57],"suffered":[55],"by":[56],"logic":[58],"gates":[59],"while":[60],"TDCs":[62],"are":[63],"used":[64,101],"track":[66],"these":[67],"across":[69],"chip":[71,91,98],"modify":[73],"in":[77,88],"order":[78],"allocate":[80],"them.":[81],"proposed":[83],"has":[85,99],"been":[86,100],"implemented":[87],"silicon":[90],"using":[92],"65nm":[94],"process.":[95],"fabricated":[97],"test":[103],"adaptive":[106],"capabilities":[107],"under":[108],"SSHet":[109],"voltage":[110,130],"variations.":[111,131],"Measurement":[112],"results":[113],"show":[114],"that":[115],"it":[116],"effectively":[117],"length,":[121],"hence":[123],"frequency,":[126],"supply":[129]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
