{"id":"https://openalex.org/W2355943008","doi":"https://doi.org/10.1145/2902961.2903002","title":"Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level","display_name":"Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level","publication_year":2016,"publication_date":"2016-05-13","ids":{"openalex":"https://openalex.org/W2355943008","doi":"https://doi.org/10.1145/2902961.2903002","mag":"2355943008"},"language":"en","primary_location":{"id":"doi:10.1145/2902961.2903002","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2902961.2903002","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032076594","display_name":"Wei Wei","orcid":"https://orcid.org/0009-0002-9368-3463"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wei Wei","raw_affiliation_strings":["Northeastern University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009094960","display_name":"Kazuteru Namba","orcid":"https://orcid.org/0000-0002-8316-7281"},"institutions":[{"id":"https://openalex.org/I159385669","display_name":"Chiba University","ror":"https://ror.org/01hjzeq58","country_code":"JP","type":"education","lineage":["https://openalex.org/I159385669"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuteru Namba","raw_affiliation_strings":["Chiba University, Chiba, Japan"],"affiliations":[{"raw_affiliation_string":"Chiba University, Chiba, Japan","institution_ids":["https://openalex.org/I159385669"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001979328","display_name":"Fabrizio Lombardi","orcid":"https://orcid.org/0000-0003-3152-3245"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fabrizio Lombardi","raw_affiliation_strings":["Northeastern University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5032076594"],"corresponding_institution_ids":["https://openalex.org/I12912129"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.03498213,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"125","last_page":"128"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8174597024917603},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7050656080245972},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5547540783882141},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5128507614135742},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.49636727571487427},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48815256357192993},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4832059144973755},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.48000138998031616},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46498343348503113},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4315755367279053},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.38482409715652466},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.367995947599411},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20169219374656677}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8174597024917603},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7050656080245972},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5547540783882141},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5128507614135742},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.49636727571487427},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48815256357192993},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4832059144973755},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.48000138998031616},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46498343348503113},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4315755367279053},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.38482409715652466},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.367995947599411},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20169219374656677},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2902961.2903002","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2902961.2903002","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 26th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1492601037","https://openalex.org/W1555915743","https://openalex.org/W1966565831","https://openalex.org/W1980364632","https://openalex.org/W2001683097","https://openalex.org/W2033811947","https://openalex.org/W2038061869","https://openalex.org/W2063779099","https://openalex.org/W2075079194","https://openalex.org/W2105102111","https://openalex.org/W2144308571","https://openalex.org/W2147539449","https://openalex.org/W2552410476","https://openalex.org/W3094065274","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2012518269","https://openalex.org/W2086718556","https://openalex.org/W2217292995","https://openalex.org/W2167303720","https://openalex.org/W2066160958","https://openalex.org/W2897450889","https://openalex.org/W1496086148","https://openalex.org/W2146079099","https://openalex.org/W2541463506","https://openalex.org/W1860107648"],"abstract_inverted_index":{"A":[0,30],"hybrid":[1,22,32,62,112],"memory":[2,34,76,88],"cell":[3,89],"usually":[4],"consists":[5],"of":[6,60,104],"a":[7],"Static":[8],"Random":[9,17],"Access":[10,18],"Memory":[11,19],"(SRAM)":[12],"and":[13,70,86],"an":[14,111],"embedded":[15],"Dynamic":[16],"(eDRAM)":[20],"cell;":[21],"cells":[23],"are":[24,64,92],"particularly":[25],"suitable":[26],"for":[27,108],"cache":[28,33,63],"design.":[29],"novel":[31],"scheme":[35,45,107],"(that":[36],"has":[37],"also":[38,93],"non-volatile":[39],"elements)":[40],"is":[41,46],"initially":[42],"proposed;":[43],"this":[44,96],"assessed":[47],"through":[48],"extensive":[49],"simulation":[50],"to":[51,100],"show":[52,101],"significant":[53],"improvements":[54],"in":[55],"performance.":[56],"Different":[57],"design":[58],"implementations":[59],"the":[61,75,79,87,102,105],"then":[65],"proposed":[66,106],"at":[67,95],"architectural":[68],"level":[69,97],"different":[71],"features":[72],"(such":[73],"as":[74,110],"hit":[77],"rate,":[78],"Instruction":[80],"Per":[81],"Cycle":[82],"(IPC)":[83],"access":[84,90],"pattern":[85],"time)":[91],"simulated":[94],"using":[98],"benchmarks":[99],"advantages":[103],"use":[109],"cache.":[113]},"counts_by_year":[{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
