{"id":"https://openalex.org/W2340522713","doi":"https://doi.org/10.1145/2901318.2901344","title":"Data tiering in heterogeneous memory systems","display_name":"Data tiering in heterogeneous memory systems","publication_year":2016,"publication_date":"2016-04-12","ids":{"openalex":"https://openalex.org/W2340522713","doi":"https://doi.org/10.1145/2901318.2901344","mag":"2340522713"},"language":"en","primary_location":{"id":"doi:10.1145/2901318.2901344","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2901318.2901344","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh European Conference on Computer Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029415471","display_name":"Subramanya R. Dulloor","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Subramanya R. Dulloor","raw_affiliation_strings":["Intel Labs and Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Intel Labs and Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444","https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103576955","display_name":"Amitabha Roy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amitabha Roy","raw_affiliation_strings":["Intel Labs"],"affiliations":[{"raw_affiliation_string":"Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017769766","display_name":"Zheguang Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I175594653","display_name":"John Brown University","ror":"https://ror.org/02ct41q97","country_code":"US","type":"education","lineage":["https://openalex.org/I175594653"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheguang Zhao","raw_affiliation_strings":["Brown University"],"affiliations":[{"raw_affiliation_string":"Brown University","institution_ids":["https://openalex.org/I175594653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110744540","display_name":"Narayanan Sundaram","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Narayanan Sundaram","raw_affiliation_strings":["Intel Labs"],"affiliations":[{"raw_affiliation_string":"Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111985072","display_name":"Nadathur Satish","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nadathur Satish","raw_affiliation_strings":["Intel Labs"],"affiliations":[{"raw_affiliation_string":"Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046656071","display_name":"Rajesh Sankaran","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajesh Sankaran","raw_affiliation_strings":["Intel Labs"],"affiliations":[{"raw_affiliation_string":"Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047250598","display_name":"Jeff Jackson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeff Jackson","raw_affiliation_strings":["Intel Labs"],"affiliations":[{"raw_affiliation_string":"Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111483107","display_name":"Karsten Schwan","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Karsten Schwan","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5029415471"],"corresponding_institution_ids":["https://openalex.org/I130701444","https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":29.8569,"has_fulltext":false,"cited_by_count":202,"citation_normalized_percentile":{"value":0.99917823,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.882015585899353},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7526048421859741},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.6843472719192505},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5940996408462524},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.5774366855621338},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5141909122467041},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5031108260154724},{"id":"https://openalex.org/keywords/data-center","display_name":"Data center","score":0.4946763217449188},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.49000850319862366},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.48591867089271545},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.42740046977996826},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.41233694553375244},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39599084854125977},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.30188336968421936},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.27701035141944885},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2738111615180969},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22014933824539185},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.12878316640853882}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.882015585899353},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7526048421859741},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.6843472719192505},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5940996408462524},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.5774366855621338},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5141909122467041},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5031108260154724},{"id":"https://openalex.org/C153740404","wikidata":"https://www.wikidata.org/wiki/Q671224","display_name":"Data center","level":2,"score":0.4946763217449188},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.49000850319862366},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.48591867089271545},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.42740046977996826},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.41233694553375244},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39599084854125977},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.30188336968421936},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.27701035141944885},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2738111615180969},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22014933824539185},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.12878316640853882}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2901318.2901344","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2901318.2901344","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Eleventh European Conference on Computer Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W78077100","https://openalex.org/W83339351","https://openalex.org/W1567210335","https://openalex.org/W1669357676","https://openalex.org/W1783256592","https://openalex.org/W1785664926","https://openalex.org/W1972584917","https://openalex.org/W1973718751","https://openalex.org/W1988852271","https://openalex.org/W1992755462","https://openalex.org/W2024713391","https://openalex.org/W2034102265","https://openalex.org/W2048588974","https://openalex.org/W2053076698","https://openalex.org/W2062140606","https://openalex.org/W2066636486","https://openalex.org/W2090204040","https://openalex.org/W2097077279","https://openalex.org/W2100857980","https://openalex.org/W2101196063","https://openalex.org/W2102843684","https://openalex.org/W2113637091","https://openalex.org/W2125901106","https://openalex.org/W2130264549","https://openalex.org/W2131135493","https://openalex.org/W2131413854","https://openalex.org/W2134633067","https://openalex.org/W2144518192","https://openalex.org/W2150662965","https://openalex.org/W2155309020","https://openalex.org/W2161047342","https://openalex.org/W2162288748","https://openalex.org/W2164999122","https://openalex.org/W2170616854","https://openalex.org/W2398564056","https://openalex.org/W2404397702","https://openalex.org/W2949282068","https://openalex.org/W3138135046","https://openalex.org/W3139689176","https://openalex.org/W4239813889"],"related_works":["https://openalex.org/W1030357071","https://openalex.org/W4238754064","https://openalex.org/W2340699851","https://openalex.org/W2188534734","https://openalex.org/W2546565930","https://openalex.org/W2293894704","https://openalex.org/W1981423095","https://openalex.org/W2041271371","https://openalex.org/W1928231567","https://openalex.org/W4390696710"],"abstract_inverted_index":{"Memory-based":[0],"data":[1],"center":[2,73],"applications":[3],"require":[4],"increasingly":[5],"large":[6,97,111],"memory":[7,37,93],"capacities,":[8],"but":[9,46],"face":[10],"the":[11,15,23,83,89,119],"challenges":[12],"posed":[13],"by":[14],"inherent":[16],"difficulties":[17],"in":[18,99],"scaling":[19],"DRAM":[20,40,92],"and":[21,56],"also":[22,47],"cost":[24],"of":[25,85,91,121],"DRAM.":[26],"Future":[27],"systems":[28],"are":[29,75],"attempting":[30],"to":[31,77,87,95,105,118],"address":[32],"these":[33],"demands":[34],"with":[35,41],"heterogeneous":[36],"architectures":[38],"coupling":[39],"high":[42,68],"capacity,":[43],"low":[44],"cost,":[45],"lower":[48],"performance,":[49],"non-volatile":[50],"memories":[51],"(NVM)":[52],"such":[53,122],"as":[54,66],"PCM":[55],"RRAM.":[57],"A":[58],"key":[59],"usage":[60,84],"model":[61,81],"intended":[62],"for":[63,82],"NVM":[64,86],"is":[65,103],"cheaper":[67],"capacity":[69],"volatile":[70],"memory.":[71],"Data":[72],"operators":[74],"bound":[76],"ask":[78],"whether":[79],"this":[80,107],"replace":[88],"majority":[90],"leads":[94],"a":[96,110],"slowdown":[98],"their":[100],"applications?":[101],"It":[102],"crucial":[104],"answer":[106],"question":[108],"because":[109],"performance":[112],"impact":[113],"will":[114],"be":[115],"an":[116],"impediment":[117],"adoption":[120],"systems.":[123]},"counts_by_year":[{"year":2025,"cited_by_count":16},{"year":2024,"cited_by_count":16},{"year":2023,"cited_by_count":17},{"year":2022,"cited_by_count":14},{"year":2021,"cited_by_count":30},{"year":2020,"cited_by_count":16},{"year":2019,"cited_by_count":32},{"year":2018,"cited_by_count":25},{"year":2017,"cited_by_count":29},{"year":2016,"cited_by_count":7}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
