{"id":"https://openalex.org/W2394805807","doi":"https://doi.org/10.1145/2897937.2898036","title":"Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture","display_name":"Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture","publication_year":2016,"publication_date":"2016-05-25","ids":{"openalex":"https://openalex.org/W2394805807","doi":"https://doi.org/10.1145/2897937.2898036","mag":"2394805807"},"language":"en","primary_location":{"id":"doi:10.1145/2897937.2898036","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2897937.2898036","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 53rd Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036436398","display_name":"Po-Han Wang","orcid":"https://orcid.org/0000-0002-6359-2109"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Han Wang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006434175","display_name":"Cheng\u2010Hsuan Li","orcid":"https://orcid.org/0000-0001-5059-8256"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Hsuan Li","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046948316","display_name":"Chia-Lin Yang","orcid":"https://orcid.org/0000-0003-0091-5027"},"institutions":[{"id":"https://openalex.org/I4210086894","display_name":"Research Center for Information Technology Innovation, Academia Sinica","ror":"https://ror.org/000zgvm20","country_code":"TW","type":"facility","lineage":["https://openalex.org/I4210086894","https://openalex.org/I84653119"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Lin Yang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan R.O.C. and Research Center for Information Technology Innovation, Academia Sinica, Taipei, Taiwan R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan R.O.C. and Research Center for Information Technology Innovation, Academia Sinica, Taipei, Taiwan R.O.C","institution_ids":["https://openalex.org/I4210086894"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7989429235458374},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7787612676620483},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7742753624916077},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5199795365333557},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45084550976753235},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.44134968519210815},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4385010600090027},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40738266706466675},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3648456335067749},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08089032769203186},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07076284289360046}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7989429235458374},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7787612676620483},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7742753624916077},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5199795365333557},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45084550976753235},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.44134968519210815},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4385010600090027},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40738266706466675},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3648456335067749},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08089032769203186},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07076284289360046},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2897937.2898036","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2897937.2898036","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 53rd Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.47999998927116394}],"awards":[{"id":"https://openalex.org/G262270419","display_name":null,"funder_award_id":"NTU-104R104124, 104R890822","funder_id":"https://openalex.org/F4320323900","funder_display_name":"National Taiwan University"},{"id":"https://openalex.org/G3822167473","display_name":null,"funder_award_id":"MOST-103-2622-E-002-034, MOST-104-2622-8-002-002, MOST-103-2220-E-002-005, MOST-104-2220-E-002-005","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"}],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"},{"id":"https://openalex.org/F4320323900","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1964280237","https://openalex.org/W1967474856","https://openalex.org/W1979527452","https://openalex.org/W1981756989","https://openalex.org/W2029577083","https://openalex.org/W2034256066","https://openalex.org/W2053374607","https://openalex.org/W2068241414","https://openalex.org/W2070630412","https://openalex.org/W2079248286","https://openalex.org/W2080592089","https://openalex.org/W2100011668","https://openalex.org/W2113247440","https://openalex.org/W2118703320","https://openalex.org/W2138146350","https://openalex.org/W2143773524","https://openalex.org/W2162639668","https://openalex.org/W2166263440","https://openalex.org/W2997147979","https://openalex.org/W4253438286"],"related_works":["https://openalex.org/W2549803267","https://openalex.org/W2497617944","https://openalex.org/W2167303720","https://openalex.org/W1563139915","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W4256652509","https://openalex.org/W2109715593","https://openalex.org/W2081416538","https://openalex.org/W2140219379"],"abstract_inverted_index":{"Shared":[0],"last-level":[1],"cache":[2],"(LLC)":[3],"management":[4],"is":[5],"a":[6,52,60,69],"critical":[7],"design":[8],"issue":[9],"for":[10],"heterogeneous":[11],"multi-cores.":[12],"In":[13],"this":[14],"paper,":[15],"we":[16,50],"observe":[17],"two":[18],"major":[19],"challenges:":[20],"the":[21,37,66,75,83,95],"contribution":[22],"of":[23],"LLC":[24,76],"latency":[25,39],"to":[26,43,64,73],"overall":[27,47,84],"performance":[28],"varies":[29],"among":[30],"applications/cores":[31],"and":[32,68],"also":[33],"across":[34],"time;":[35],"overlooking":[36],"off-chip":[38],"factor":[40],"often":[41],"leads":[42],"adverse":[44],"effects":[45],"on":[46,88],"performance.":[48],"Hence,":[49],"propose":[51],"Latency":[53],"Sensitivity-based":[54],"Cache":[55],"Partitioning":[56],"(LSP)":[57],"framework,":[58],"including":[59],"lightweight":[61],"runtime":[62],"mechanism":[63],"quantify":[65],"latency-sensitivity":[67],"new":[70],"cost":[71],"function":[72],"guide":[74],"partitioning.":[77],"Results":[78],"show":[79],"that":[80],"LSP":[81],"improves":[82],"throughput":[85],"by":[86],"8%":[87],"average":[89],"(27%":[90],"at":[91],"most),":[92],"compared":[93],"with":[94],"state-of-the-art":[96],"partitioning":[97],"mechanism,":[98],"TAP.":[99]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}