{"id":"https://openalex.org/W2398862834","doi":"https://doi.org/10.1145/2897937.2898005","title":"Designing approximate circuits using clock overgating","display_name":"Designing approximate circuits using clock overgating","publication_year":2016,"publication_date":"2016-05-25","ids":{"openalex":"https://openalex.org/W2398862834","doi":"https://doi.org/10.1145/2897937.2898005","mag":"2398862834"},"language":"en","primary_location":{"id":"doi:10.1145/2897937.2898005","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2897937.2898005","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=2898005&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 53rd Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://dl.acm.org/ft_gateway.cfm?id=2898005&type=pdf","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100327649","display_name":"Younghoon Kim","orcid":"https://orcid.org/0000-0002-0773-2146"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Younghoon Kim","raw_affiliation_strings":["Purdue University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010094713","display_name":"Swagath Venkataramani","orcid":"https://orcid.org/0000-0002-0470-6364"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swagath Venkataramani","raw_affiliation_strings":["Purdue University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0002-0735-9695"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Purdue University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065766721","display_name":"Anand Raghunathan","orcid":"https://orcid.org/0000-0002-4624-564X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anand Raghunathan","raw_affiliation_strings":["Purdue University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":22,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7893239259719849},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5765405893325806},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.541920006275177},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5057764053344727},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.47659891843795776},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4741515517234802},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46031567454338074},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4570664167404175},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.45242181420326233},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.41226115822792053},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.39467865228652954},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38756197690963745},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2682194113731384},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21752366423606873},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14396455883979797},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09887418150901794}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7893239259719849},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5765405893325806},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.541920006275177},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5057764053344727},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.47659891843795776},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4741515517234802},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46031567454338074},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4570664167404175},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.45242181420326233},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.41226115822792053},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.39467865228652954},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38756197690963745},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2682194113731384},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21752366423606873},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14396455883979797},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09887418150901794},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2897937.2898005","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2897937.2898005","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=2898005&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 53rd Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/2897937.2898005","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2897937.2898005","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=2898005&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 53rd Annual Design Automation Conference","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[{"id":"https://openalex.org/G1447877572","display_name":"CSR: Small: Quality Programmable Processing Platforms for Approximate Computing","funder_award_id":"1423290","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2398862834.pdf","grobid_xml":"https://content.openalex.org/works/W2398862834.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W1579004116","https://openalex.org/W1965672260","https://openalex.org/W1967519200","https://openalex.org/W1986192284","https://openalex.org/W1988290377","https://openalex.org/W1996431812","https://openalex.org/W2003957094","https://openalex.org/W2005506050","https://openalex.org/W2010468809","https://openalex.org/W2045294186","https://openalex.org/W2104578404","https://openalex.org/W2105216798","https://openalex.org/W2106360508","https://openalex.org/W2106484393","https://openalex.org/W2109489315","https://openalex.org/W2118683741","https://openalex.org/W2121069160","https://openalex.org/W2140145164","https://openalex.org/W2142096775","https://openalex.org/W2153848924","https://openalex.org/W2157204696","https://openalex.org/W3147234326"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2308963021","https://openalex.org/W2052455055","https://openalex.org/W2090237663","https://openalex.org/W2076992934","https://openalex.org/W1989324326","https://openalex.org/W4200240321","https://openalex.org/W2158864330","https://openalex.org/W2224788396","https://openalex.org/W2520965597"],"abstract_inverted_index":{"Approximate":[0],"computing":[1,11],"is":[2,63,85],"an":[3,26,127],"emerging":[4],"paradigm":[5],"to":[6,20,64,69,87,116,125],"improve":[7],"the":[8,15,49,55,66,74,82,94,97,111,117,159,169],"efficiency":[9],"of":[10,18,51,158,172,184,193],"systems":[12],"by":[13,180],"leveraging":[14],"intrinsic":[16],"resilience":[17],"applications":[19],"their":[21,88],"computations":[22],"being":[23],"executed":[24],"in":[25,73,80,93,101,204],"approximate":[27,32,52,182],"manner.":[28],"Prior":[29],"efforts":[30],"on":[31,38,195],"hardware":[33],"design":[34,50],"have":[35],"largely":[36],"focused":[37],"circuit-level":[39],"techniques.":[40],"We":[41,120,176],"propose":[42],"a":[43,106,122],"new":[44],"approach,":[45],"clock":[46,67,95,178],"overgating,":[47,148],"for":[48,131,163,200],"circuits":[53],"at":[54],"Register":[56],"Transfer":[57],"Level":[58],"(RTL).":[59],"The":[60],"key":[61,144],"idea":[62],"gate":[65],"signal":[68],"selected":[70],"Flip-Flops":[71],"(FFs)":[72],"circuit,":[75],"even":[76],"during":[77],"execution":[78],"cycles":[79],"which":[81],"circuit":[83,118,134,160],"functionality":[84],"sensitive":[86],"state.":[89],"This":[90],"saves":[91],"power":[92],"tree,":[96],"FF":[98,113],"itself":[99],"and":[100,135,154,189],"its":[102],"downstream":[103],"logic,":[104],"while":[105],"quality":[107,136,206],"loss":[108,203],"ensues":[109],"if":[110],"erroneous":[112],"state":[114],"propagates":[115],"output.":[119],"develop":[121,142],"systematic":[123],"methodology":[124],"identify":[126],"energy-efficient":[128],"overgating":[129,152,164,174,179],"configuration":[130],"any":[132],"given":[133],"constraint.":[137],"Towards":[138],"this":[139],"end,":[140],"we":[141],"3":[143],"strategies":[145],"---":[146,165],"significance-based":[147],"grouping":[149],"FFs":[150],"into":[151],"islands,":[153],"utilizing":[155],"internal":[156],"signals":[157],"as":[161],"triggers":[162],"that":[166],"efficiently":[167],"prune":[168],"large":[170],"space":[171],"possible":[173],"configurations.":[175],"evaluate":[177],"designing":[181],"versions":[183],"6":[185],"machine":[186],"learning":[187],"accelerators,":[188],"demonstrate":[190],"energy":[191],"benefits":[192],"1.36\u00d7":[194],"average":[196],"(and":[197],"upto":[198],"1.80\u00d7)":[199],"negligible":[201],"(<0.5%)":[202],"application":[205],"(classification":[207],"accuracy).":[208]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
