{"id":"https://openalex.org/W2333469681","doi":"https://doi.org/10.1145/2872334.2872349","title":"Construction of Latency-Bounded Clock Trees","display_name":"Construction of Latency-Bounded Clock Trees","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2333469681","doi":"https://doi.org/10.1145/2872334.2872349","mag":"2333469681"},"language":"en","primary_location":{"id":"doi:10.1145/2872334.2872349","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2872334.2872349","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=2872349&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 on International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://dl.acm.org/ft_gateway.cfm?id=2872349&type=pdf","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014892277","display_name":"Rickard Ewetz","orcid":"https://orcid.org/0000-0002-4183-6926"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Rickard Ewetz","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026009848","display_name":"Chuan Yean Tan","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chuan Yean Tan","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5014892277"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":0.3718,"has_fulltext":true,"cited_by_count":5,"citation_normalized_percentile":{"value":0.64417535,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"81","last_page":"88"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7543557286262512},{"id":"https://openalex.org/keywords/bounding-overwatch","display_name":"Bounding overwatch","score":0.6980860829353333},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6564238667488098},{"id":"https://openalex.org/keywords/bounded-function","display_name":"Bounded function","score":0.6445351839065552},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5210132598876953},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5143864750862122},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41687989234924316},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.385511577129364},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.30657410621643066},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13474079966545105}],"concepts":[{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7543557286262512},{"id":"https://openalex.org/C63584917","wikidata":"https://www.wikidata.org/wiki/Q333286","display_name":"Bounding overwatch","level":2,"score":0.6980860829353333},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6564238667488098},{"id":"https://openalex.org/C34388435","wikidata":"https://www.wikidata.org/wiki/Q2267362","display_name":"Bounded function","level":2,"score":0.6445351839065552},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5210132598876953},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5143864750862122},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41687989234924316},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.385511577129364},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.30657410621643066},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13474079966545105},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2872334.2872349","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2872334.2872349","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=2872349&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 on International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/2872334.2872349","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2872334.2872349","pdf_url":"http://dl.acm.org/ft_gateway.cfm?id=2872349&type=pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 on International Symposium on Physical Design","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2692225030","display_name":"SHF:  Small:  Synthesis of Robust Clock Networks for Multiple-Corner Multiple-Mode Designs","funder_award_id":"1527562","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G2734489678","display_name":null,"funder_award_id":"CFF-1065318 and CFF-1514371","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6787993161","display_name":null,"funder_award_id":"1065318","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2333469681.pdf","grobid_xml":"https://content.openalex.org/works/W2333469681.grobid-xml"},"referenced_works_count":17,"referenced_works":["https://openalex.org/W1983206124","https://openalex.org/W1985843314","https://openalex.org/W1996150371","https://openalex.org/W2025594056","https://openalex.org/W2041950850","https://openalex.org/W2060463852","https://openalex.org/W2113682107","https://openalex.org/W2120116751","https://openalex.org/W2122944491","https://openalex.org/W2125692303","https://openalex.org/W2170009145","https://openalex.org/W2293567771","https://openalex.org/W2510949177","https://openalex.org/W2955479062","https://openalex.org/W3145128584","https://openalex.org/W4250702245","https://openalex.org/W4254506919"],"related_works":["https://openalex.org/W4232019485","https://openalex.org/W2156857157","https://openalex.org/W2028052815","https://openalex.org/W2171197263","https://openalex.org/W2076413498","https://openalex.org/W2164834710","https://openalex.org/W2123512677","https://openalex.org/W2374577476","https://openalex.org/W4327499872","https://openalex.org/W2116259070"],"abstract_inverted_index":{"Clock":[0],"trees":[1,158,166],"must":[2],"be":[3,85,108],"constructed":[4,86,167],"to":[5,30,93,137,144,164],"function":[6],"even":[7],"under":[8],"the":[9,16,23,27,37,41,45,60,68,72,88,94,104,114,150],"influence":[10],"of":[11,18,44,62,65,79,96,99,122,147,154],"on-chip":[12],"variations":[13],"(OCV).":[14],"Bounding":[15],"latency":[17,38,54,78],"a":[19,53,63,80,100,118,123,131,145],"clock":[20,81,125,132,140,157,165],"tree,":[21],"i.e.,":[22],"maximum":[24,42],"delay":[25],"from":[26,87],"tree":[28,82,126,133],"root":[29],"any":[31],"sequential":[32],"element,":[33],"is":[34,74,91,152],"important":[35],"because":[36],"correlates":[39],"with":[40],"magnitude":[43],"skews":[46],"caused":[47],"by":[48],"OCV.":[49],"In":[50],"this":[51],"paper,":[52],"constraint":[55],"graph":[56],"(LCG)":[57],"that":[58,83,120,159],"captures":[59],"latencies":[61],"set":[64,146],"subtrees":[66,73,90],"and":[67,130],"skew":[69],"constraints":[70],"between":[71],"introduced.":[75],"The":[76],"minimum":[77],"can":[84,107],"corresponding":[89],"equal":[92],"(negative":[95],"the)":[97],"length":[98],"shortest":[101],"path":[102],"in":[103,110,168],"LCG,":[105,115],"which":[106],"computed":[109],"$O(VE)$.":[111],"Based":[112],"on":[113],"we":[116],"propose":[117],"framework":[119,151],"consists":[121],"latency-aware":[124],"synthesis":[127],"(CTS)":[128],"phase":[129,136],"optimization":[134],"(CTO)":[135],"construct":[138],"latency-bounded":[139,156],"trees.":[141],"When":[142],"applied":[143],"synthesized":[148],"circuits,":[149],"capable":[153],"constructing":[155],"have":[160],"higher":[161],"yield":[162],"compared":[163],"previous":[169],"studies.":[170]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}
