{"id":"https://openalex.org/W2320475489","doi":"https://doi.org/10.1145/2872334.2872336","title":"Challenges and Opportunities with Place and Route of Modern FPGA Designs","display_name":"Challenges and Opportunities with Place and Route of Modern FPGA Designs","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2320475489","doi":"https://doi.org/10.1145/2872334.2872336","mag":"2320475489"},"language":"en","primary_location":{"id":"doi:10.1145/2872334.2872336","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2872334.2872336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 on International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075317437","display_name":"Raymond Nijssen","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Raymond Nijssen","raw_affiliation_strings":["Achronix Semiconductor Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Achronix Semiconductor Corporation, Santa Clara, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5075317437"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5494631,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"57","last_page":"57"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.80180823802948},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7600548267364502},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7507365942001343},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6712990999221802},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6135061383247375},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.6039500832557678},{"id":"https://openalex.org/keywords/predictability","display_name":"Predictability","score":0.5852710604667664},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49842071533203125},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4895420968532562},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4608018696308136},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.41212159395217896},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.15325674414634705},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09038117527961731}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.80180823802948},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7600548267364502},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7507365942001343},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6712990999221802},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6135061383247375},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.6039500832557678},{"id":"https://openalex.org/C197640229","wikidata":"https://www.wikidata.org/wiki/Q2534066","display_name":"Predictability","level":2,"score":0.5852710604667664},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49842071533203125},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4895420968532562},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4608018696308136},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.41212159395217896},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.15325674414634705},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09038117527961731},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2872334.2872336","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2872334.2872336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 on International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3200538824","https://openalex.org/W2097839191","https://openalex.org/W1561071093","https://openalex.org/W2070693700","https://openalex.org/W2132668926","https://openalex.org/W2030503305","https://openalex.org/W4391382037","https://openalex.org/W2227166741","https://openalex.org/W4386859294","https://openalex.org/W2380223518"],"abstract_inverted_index":{"In":[0],"the":[1],"last":[2],"decade":[3],"place":[4],"and":[5,47,61,71,87,93],"route":[6],"algorithms":[7,37],"used":[8,21],"for":[9],"large":[10],"high":[11],"performance":[12,49],"FPGA":[13,28],"designs":[14,51],"have":[15],"been":[16],"successfully":[17],"adapted":[18],"from":[19],"those":[20],"in":[22,84],"ASIC":[23],"design":[24,67],"flows.":[25],"All":[26],"major":[27],"tool":[29],"sets":[30],"now":[31],"use":[32],"advanced":[33],"analytical":[34],"global":[35],"placement":[36],"with":[38,52],"sophisticated":[39],"cell":[40],"clustering.":[41],"Thanks":[42],"to":[43,59,77,90],"this,":[44],"fast":[45],"runtimes":[46],"predictable":[48],"on":[50],"millions":[53],"of":[54,74],"placeable":[55],"objects":[56],"empower":[57],"designers":[58,79],"quickly":[60],"often":[62],"evaluate":[63],"their":[64,85],"decisions.":[65],"Fast":[66],"flow":[68],"turn-around":[69],"times":[70],"predictability":[72],"are":[73],"tremendous":[75],"value":[76],"help":[78],"improve":[80],"timing":[81],"closure":[82],"problems":[83],"designs,":[86],"accommodate":[88],"them":[89],"floorplanning":[91],"constraints":[92],"congestion":[94],"bottlenecks.":[95]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
