{"id":"https://openalex.org/W2313278055","doi":"https://doi.org/10.1145/2871737","title":"Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis","display_name":"Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis","publication_year":2016,"publication_date":"2016-02-26","ids":{"openalex":"https://openalex.org/W2313278055","doi":"https://doi.org/10.1145/2871737","mag":"2313278055"},"language":"en","primary_location":{"id":"doi:10.1145/2871737","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2871737","pdf_url":null,"source":{"id":"https://openalex.org/S136160450","display_name":"ACM Transactions on Embedded Computing Systems","issn_l":"1539-9087","issn":["1539-9087","1558-3465"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Embedded Computing Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://porto.polito.it/2648227/","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027243148","display_name":"Shahzad Ahmad Butt","orcid":"https://orcid.org/0000-0002-9747-221X"},"institutions":[{"id":"https://openalex.org/I201384688","display_name":"National University of Computer and Emerging Sciences","ror":"https://ror.org/003eyb898","country_code":"PK","type":"education","lineage":["https://openalex.org/I201384688"]}],"countries":["PK"],"is_corresponding":true,"raw_author_name":"Shahzad Ahmad Butt","raw_affiliation_strings":["National University of Computer and Emerging Sciences Lahore, Lahore, Pakistan"],"raw_orcid":"https://orcid.org/0000-0002-9747-221X","affiliations":[{"raw_affiliation_string":"National University of Computer and Emerging Sciences Lahore, Lahore, Pakistan","institution_ids":["https://openalex.org/I201384688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026581196","display_name":"Mehdi Roozmeh","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mehdi Roozmeh","raw_affiliation_strings":["Politecnico di Torino, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luciano Lavagno","raw_affiliation_strings":["Politecnico di Torino, Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5027243148"],"corresponding_institution_ids":["https://openalex.org/I201384688"],"apc_list":null,"apc_paid":null,"fwci":0.6405,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65892743,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"15","issue":"2","first_page":"1","last_page":"28"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8531171083450317},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7600688934326172},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6970088481903076},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6648709774017334},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5235143303871155},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4814842939376831},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47868257761001587},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45053809881210327},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.4485512971878052},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.4366898536682129},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4153246581554413},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4103577136993408},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14741775393486023}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8531171083450317},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7600688934326172},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6970088481903076},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6648709774017334},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5235143303871155},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4814842939376831},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47868257761001587},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45053809881210327},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.4485512971878052},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.4366898536682129},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4153246581554413},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4103577136993408},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14741775393486023},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2871737","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2871737","pdf_url":null,"source":{"id":"https://openalex.org/S136160450","display_name":"ACM Transactions on Embedded Computing Systems","issn_l":"1539-9087","issn":["1539-9087","1558-3465"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Embedded Computing Systems","raw_type":"journal-article"},{"id":"pmh:oai:porto.polito.it:2648227","is_oa":true,"landing_page_url":"http://porto.polito.it/2648227/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1539-9087","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:porto.polito.it:2648227","is_oa":true,"landing_page_url":"http://porto.polito.it/2648227/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1539-9087","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1492367846","https://openalex.org/W1505830007","https://openalex.org/W1974944762","https://openalex.org/W2029518208","https://openalex.org/W2042762783","https://openalex.org/W2081764996","https://openalex.org/W2098682737","https://openalex.org/W2101555824","https://openalex.org/W2114435074","https://openalex.org/W2119674509","https://openalex.org/W2127844926","https://openalex.org/W2140837302","https://openalex.org/W2153929699","https://openalex.org/W2156359858","https://openalex.org/W2156540652","https://openalex.org/W2161112535","https://openalex.org/W2161294182","https://openalex.org/W2167060712","https://openalex.org/W2504581551","https://openalex.org/W4231605664","https://openalex.org/W4251128420"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2269990635","https://openalex.org/W4312985392","https://openalex.org/W2108242004","https://openalex.org/W2042762783","https://openalex.org/W1978911128","https://openalex.org/W4283730710","https://openalex.org/W4281784598","https://openalex.org/W2921149022","https://openalex.org/W4313484792"],"abstract_inverted_index":{"Model-based":[0,30],"hardware":[1,12,33,95,103],"design":[2,31,79,99,185],"allows":[3],"one":[4,18],"to":[5,10,71,180,183],"map":[6],"a":[7,38,139,162],"single":[8],"model":[9,121],"multiple":[11,181],"and/or":[13],"software":[14],"architectures,":[15],"essentially":[16],"eliminating":[17],"of":[19,23,41,111,133],"the":[20,75,117,131,197],"major":[21],"limitations":[22],"manual":[24],"coding":[25],"in":[26,85,196],"C":[27,86],"or":[28],"RTL.":[29],"for":[32,48,90,124,148,193],"implementation":[34,104],"has":[35],"traditionally":[36],"offered":[37],"limited":[39],"set":[40],"microarchitectures,":[42],"which":[43],"are":[44,83,88],"typically":[45],"suitable":[46],"only":[47],"some":[49],"application":[50],"scenarios.":[51],"In":[52],"this":[53],"article":[54],"we":[55,137],"illustrate":[56],"how":[57],"digital":[58],"signal":[59],"processing":[60],"(DSP)":[61],"algorithms":[62],"can":[63,170,177],"be":[64,72,178],"modeled":[65,138],"as":[66,188,190],"flexible":[67,172],"intellectual":[68,165],"property":[69,166],"blocks":[70,82,175],"used":[73,123,192],"within":[74],"popular":[76],"Simulink":[77,198],"model-based":[78],"environment.":[80,199],"These":[81],"written":[84],"and":[87,94,102,126,145,156],"designed":[89],"both":[91],"functional":[92,194],"simulation":[93,125,195],"implementation,":[96],"including":[97],"architectural":[98],"space":[100,186],"exploration":[101,187],"through":[105],"high-level":[106,127],"synthesis.":[107,128],"A":[108],"key":[109],"advantage":[110],"our":[112,134],"modeling":[113],"approach":[114],"is":[115,122],"that":[116,169,176],"very":[118,153],"same":[119],"bit-accurate":[120],"To":[129],"prove":[130],"feasibility":[132],"proposed":[135],"approach,":[136],"fast":[140],"Fourier":[141],"transform":[142],"(FFT)":[143],"algorithm":[144],"synthesized":[146],"it":[147],"different":[149,154],"DSP":[150],"applications":[151],"with":[152],"performance":[155],"cost":[157],"requirements.":[158],"We":[159],"also":[160],"implemented":[161],"high-level-synthesis":[163],"(HLS)":[164],"(IP)":[167],"generator":[168],"generate":[171],"FFT":[173],"HLS-IP":[174],"mapped":[179],"micro-/macroarchitectures,":[182],"enable":[184],"well":[189],"being":[191]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}